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zephyr/ext/hal/openisa/vega_sdk_riscv/Kconfig

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soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 10:40:57 +01:00
# Copyright (c) 2018 Foundries.io
#
# SPDX-License-Identifier: Apache-2.0
menuconfig VEGA_SDK_HAL
bool "RV32M1 VEGA SDK support"
depends on SOC_OPENISA_RV32M1_RISCV32
serial: RV32M1: introduce lpuart driver / DT bindings Add a UART driver. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-07 19:13:52 +01:00
config HAS_RV32M1_LPUART
bool
help
Set if the low power uart (LPUART) module is present in the SoC.
drivers: i2c: rv32m1: add I2C driver for the RV32M1 RI5CY SoC Add driver and device tree binding for the Low Power Inter-Integrated Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-04-01 21:09:44 +02:00
config HAS_RV32M1_LPI2C
bool
help
Set if the low power i2c (LPI2C) module is present in the SoC.
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