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zephyr/arch/arm/core/CMakeLists.txt

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 15:08:09 +02:00
# SPDX-License-Identifier: Apache-2.0
arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files. Normally a syscall would check the current privilege level and then decide to go to _impl_<syscall> directly or go through a _handler_<syscall>. __ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will make all the system calls from the arch files directly link to the _impl_<syscall>. Thereby reducing the overhead of checking the privileges. In the previous implementation all the source files would be compiled by zephyr_source() rule. This means that zephyr_* is a catchall CMake library for source files that can be built purely with the include paths, defines, and other compiler flags that all zephyr source files uses. This states that adding one extra compiler flag for only one complete directory would fail. This limitation can be overcome by using zephyr_libray* APIs. This creates a library for the required directories and it also supports directory level properties. Hence we use zephyr_library* to create a new library with macro _ZEPHYR_SUPERVISOR_ for the optimization. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-03-28 12:00:20 +02:00
zephyr_library()
zephyr_library_sources(
Introduce cmake-based rewrite of KBuild Introducing CMake is an important step in a larger effort to make Zephyr easy to use for application developers working on different platforms with different development environment needs. Simplified, this change retains Kconfig as-is, and replaces all Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild offers is replaced by a set of CMake extentions. These extentions have either provided simple one-to-one translations of KBuild features or introduced new concepts that replace KBuild concepts. This is a breaking change for existing test infrastructure and build scripts that are maintained out-of-tree. But for FW itself, no porting should be necessary. For users that just want to continue their work with minimal disruption the following should suffice: Install CMake 3.8.2+ Port any out-of-tree Makefiles to CMake. Learn the absolute minimum about the new command line interface: $ cd samples/hello_world $ mkdir build && cd build $ cmake -DBOARD=nrf52_pca10040 .. $ cd build $ make PR: zephyrproject-rtos#4692 docs: http://docs.zephyrproject.org/getting_started/getting_started.html Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-10-27 15:43:34 +02:00
fatal.c
arch: arm: Move nmi code for Cortex-R support This code can start out being common between Cortex-R and Cortex-M. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2018-06-25 16:41:11 +02:00
nmi.c
nmi_on_reset.S
Introduce cmake-based rewrite of KBuild Introducing CMake is an important step in a larger effort to make Zephyr easy to use for application developers working on different platforms with different development environment needs. Simplified, this change retains Kconfig as-is, and replaces all Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild offers is replaced by a set of CMake extentions. These extentions have either provided simple one-to-one translations of KBuild features or introduced new concepts that replace KBuild concepts. This is a breaking change for existing test infrastructure and build scripts that are maintained out-of-tree. But for FW itself, no porting should be necessary. For users that just want to continue their work with minimal disruption the following should suffice: Install CMake 3.8.2+ Port any out-of-tree Makefiles to CMake. Learn the absolute minimum about the new command line interface: $ cd samples/hello_world $ mkdir build && cd build $ cmake -DBOARD=nrf52_pca10040 .. $ cd build $ make PR: zephyrproject-rtos#4692 docs: http://docs.zephyrproject.org/getting_started/getting_started.html Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-10-27 15:43:34 +02:00
)
treewide: Use CONFIG_CPP instead of CONFIG_CPLUSPLUS This commit updates all in-tree code to use `CONFIG_CPP` instead of `CONFIG_CPLUSPLUS`, which is now deprecated. Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
2022-12-08 22:16:44 +01:00
zephyr_library_sources_ifdef(CONFIG_CPP __aeabi_atexit.c)
arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files. Normally a syscall would check the current privilege level and then decide to go to _impl_<syscall> directly or go through a _handler_<syscall>. __ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will make all the system calls from the arch files directly link to the _impl_<syscall>. Thereby reducing the overhead of checking the privileges. In the previous implementation all the source files would be compiled by zephyr_source() rule. This means that zephyr_* is a catchall CMake library for source files that can be built purely with the include paths, defines, and other compiler flags that all zephyr source files uses. This states that adding one extra compiler flag for only one complete directory would fail. This limitation can be overcome by using zephyr_libray* APIs. This creates a library for the required directories and it also supports directory level properties. Hence we use zephyr_library* to create a new library with macro _ZEPHYR_SUPERVISOR_ for the optimization. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-03-28 12:00:20 +02:00
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
arch: arm: Remove aarch32 directory It doesn't make sense to keep the aarch32 directory in the 'arch/arm/core' directory as the aarch64 has been moved out. This commit introduces the following major changes. 1. Move all directories and files in 'arch/arm/core/aarch32' to 'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory. 2. Move all directories and files in 'arch/include/aarch32' to 'arch/include' and remove the 'arch/include/aarch32' directory. 3. Remove the nested including in the 'arch/include/kernel_arch_func.h' and 'arch/include/offsets_short_arch.h' header files. 4. Change the path string which is influenced by the changement 1 and 2. Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-07-04 08:21:40 +02:00
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files. Normally a syscall would check the current privilege level and then decide to go to _impl_<syscall> directly or go through a _handler_<syscall>. __ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will make all the system calls from the arch files directly link to the _impl_<syscall>. Thereby reducing the overhead of checking the privileges. In the previous implementation all the source files would be compiled by zephyr_source() rule. This means that zephyr_* is a catchall CMake library for source files that can be built purely with the include paths, defines, and other compiler flags that all zephyr source files uses. This states that adding one extra compiler flag for only one complete directory would fail. This limitation can be overcome by using zephyr_libray* APIs. This creates a library for the required directories and it also supports directory level properties. Hence we use zephyr_library* to create a new library with macro _ZEPHYR_SUPERVISOR_ for the optimization. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-03-28 12:00:20 +02:00
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
arch: arm: aarch32: Add ability to generate zImage header The image header is compatible for zImage(32) protocol. Offset Value Description 0x24 0x016F2818 Magic number to identify ARM Linux zImage 0x28 start address The address the zImage starts at 0x2C end address The address the zImage ends at As Zephyr can be built with a fixed load address, Xen/Uboot can read the image header and decide where to copy the Zephyr image. Also, it is to be noted that for AArch32 A/R, the vector table should be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815, G8.2.168, VBAR, Vector Base Address Register :- Bits[4:0] = RES0. For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table Offset Register), Bits [6:0] = RES0. As zImage header occupies 0x30 bytes, thus it is necessary to align the vector table base address to 0x80 (which satisfies both VBAR and VTOR requirements). Also, it is to be noted that not all the AArch32 M class have VTOR, thus ARM_ZIMAGE_HEADER header depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR. The reason being the processors which does not have VBAR or VTOR, needs to have exception vector table at a fixed address in the beginning of ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt) . They cannot support any headers. Also, the first instruction in zImage header is to branch to the kernel start address. This is to support booting in situations where the zImage header need not be parsed. In case of Arm v8M, the first two entries in the reset vector should be "Initial value for the main stack pointer on reset" and "Start address for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30, Vector tables). In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table), the first entry is "SP_main. This is the reset value of the Main stack pointer.". Thus when v7M or v8M starts from reset, it expects to see these values at the default reset vector location. See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526) "On powerup or reset, the processor uses the entry at offset 0 as the initial value for SP_main..." Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2022-12-14 13:46:53 +01:00
zephyr_library_sources_ifdef(CONFIG_ARM_ZIMAGE_HEADER header.S)
llext: Linkable loadable extensions Adds the linkable loadable extensions (llext) subsystem which provides functionality for reading, parsing, and linking ELF encoded executable code into a managed extension to the running elf base image. A loader interface, and default buffer loader implementation, make available to the llext subsystem the elf data. A simple management API provide the ability to load and unload extensions as needed. A shell interface for extension loading and unloading makes it easy to try. Adds initial support for armv7 thumb built elfs with very specific compiler flags. Signed-off-by: Tom Burdick <thomas.burdick@intel.com> Co-authored-by: Chen Peng1 <peng1.chen@intel.com> Co-authored-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-09-27 15:10:10 +02:00
zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
arm: debug: Add GDB stub for aarch32 This commit adds implementation of GDB stub for 32-bit ARM. It has been tested only on the Zynq-7000 SoC and I would like to get any feedback from others. The stub still has these issues: - To implement single stepping, it uses instruction address mismatch breakpoint, as recommended in ARMv7 reference. The breakpoint control register is configured (the state control fields) for the "PL0, Supervisor and System modes only" option. Otherwise the breakpoint would also halt the processor in abort mode, in which the stub loop runs. Zephyr kernel runs in the system mode. This works well until the kernel enables interrupts, as interrupt handlers typically run in Supervisor mode. Single stepping therefore sometimes "catches" a handler instead of the next application instruction. I have not tried User mode, because Cortex-A SoCs do not appear to have the ARCH_HAS_USERSPACE flag. Cc: Michal Sojka <michal.sojka@cvut.cz> Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
2023-04-08 20:06:23 +02:00
zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
Introduce cmake-based rewrite of KBuild Introducing CMake is an important step in a larger effort to make Zephyr easy to use for application developers working on different platforms with different development environment needs. Simplified, this change retains Kconfig as-is, and replaces all Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild offers is replaced by a set of CMake extentions. These extentions have either provided simple one-to-one translations of KBuild features or introduced new concepts that replace KBuild concepts. This is a breaking change for existing test infrastructure and build scripts that are maintained out-of-tree. But for FW itself, no porting should be necessary. For users that just want to continue their work with minimal disruption the following should suffice: Install CMake 3.8.2+ Port any out-of-tree Makefiles to CMake. Learn the absolute minimum about the new command line interface: $ cd samples/hello_world $ mkdir build && cd build $ cmake -DBOARD=nrf52_pca10040 .. $ cd build $ make PR: zephyrproject-rtos#4692 docs: http://docs.zephyrproject.org/getting_started/getting_started.html Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-10-27 15:43:34 +02:00
add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
arch: arm: Define & implement API for test target (Non-Secure) This commit defines and implements an internal ARMv8-M API that allows the user to evaluate access permissions of memory locations, based on the ARMv8-M Test Target (TT) instruction support. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-28 15:30:40 +02:00
add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
arch: arm: configure non-secure registers from secure firmware Define and implement an API to configure the Non-Secure instances of core registers in ARM Cortex-M23 and Cortex-M33. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-22 15:26:26 +01:00
add_subdirectory_ifdef(CONFIG_ARM_SECURE_FIRMWARE cortex_m/tz)
arch: arm: core: tz: Linking of secure entry functions into NS firmware Add Kconfig options: - ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS - ARM_ENTRY_VENEERS_LIB_NAME Use these to link the veneers lib into the Non-Secure Firmware when needed. Also, make the path passed to the linker absolute to make it work with makefiles. Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-05-10 08:45:43 +02:00
add_subdirectory_ifdef(CONFIG_ARM_NONSECURE_FIRMWARE cortex_m/tz)
arch: arm: Add Cortex-R support This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2018-06-25 15:15:14 +02:00
arch: arm: aarch32: Move mpu code up a level Move the mpu code to the common aarch32 directory in preparation for Cortex-R mpu support Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2020-08-30 05:28:37 +02:00
add_subdirectory_ifdef(CONFIG_ARM_MPU mpu)
arch: arm: core: aarch32: introduce basic ARMv7 MMU support An initial implementation for memory management using the ARMv7 MMU. A single L1 translation table for the whole 4 GB address space is al- ways present, a configurable number of L2 page tables are linked to the L1 table based on the static memory area configuration at boot time, or whenever arch_mem_map/arch_mem_unmap are called at run-time. Currently, a CPU with the Multiprocessor Extensions and execution at PL1 are always assumed. Userspace-related features or thread stack guard pages are not yet supported. Neither are LPAE, PXN or TEX re- mapping. All mappings are currently assigned to the same domain. Re- garding the permissions model, access permissions are specified using the AP[2:1] model rather than the older AP[2:0] model, which, accor- ding to ARM's documentation, is deprecated and should no longer be used. The newer model adds some complexity when it comes to mapping pages as unaccessible (the AP[2:1] model doesn't support explicit specification of "no R, no W" permissions, it's always at least "RO"), this is accomplished by invalidating the ID bits of the respective page's PTE. Includes sources, Kconfig integration, adjusted CMakeLists and the modified linker command file (proper section alignment!). Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-07-15 10:33:58 +02:00
add_subdirectory_ifdef(CONFIG_ARM_AARCH32_MMU mmu)
arch: arm: aarch32: Move mpu code up a level Move the mpu code to the common aarch32 directory in preparation for Cortex-R mpu support Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2020-08-30 05:28:37 +02:00
arch: arm: aarch32: Change CPU_CORTEX_R kconfig option Change the CPU_CORTEX_R kconfig option to CPU_AARCH32_CORTEX_R to distinguish the armv7 version from the armv8 version of Cortex-R. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-10-30 01:24:17 +02:00
add_subdirectory_ifdef(CONFIG_CPU_AARCH32_CORTEX_R cortex_a_r)
arch: arm: core: aarch32: enable ARMv7-R/Cortex-R code for ARMv7-A/Cortex-A Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is set is also compiled if CONFIG_ARMV7_A is set. Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set. Modify source dir inclusion in CMakeLists.txt accordingly. Brief file descriptions have been updated to include Cortex-A whereever only Cortex-M and Cortex-R were mentioned so far. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-07-15 10:49:19 +02:00
add_subdirectory_ifdef(CONFIG_CPU_AARCH32_CORTEX_A cortex_a_r)
arm: linker.ld: Port the vector table to zephyr_linker_sources() Also port vector table relay. Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-11-28 16:59:15 +01:00
arch: arm: aarch32: Add ability to generate zImage header The image header is compatible for zImage(32) protocol. Offset Value Description 0x24 0x016F2818 Magic number to identify ARM Linux zImage 0x28 start address The address the zImage starts at 0x2C end address The address the zImage ends at As Zephyr can be built with a fixed load address, Xen/Uboot can read the image header and decide where to copy the Zephyr image. Also, it is to be noted that for AArch32 A/R, the vector table should be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815, G8.2.168, VBAR, Vector Base Address Register :- Bits[4:0] = RES0. For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table Offset Register), Bits [6:0] = RES0. As zImage header occupies 0x30 bytes, thus it is necessary to align the vector table base address to 0x80 (which satisfies both VBAR and VTOR requirements). Also, it is to be noted that not all the AArch32 M class have VTOR, thus ARM_ZIMAGE_HEADER header depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR. The reason being the processors which does not have VBAR or VTOR, needs to have exception vector table at a fixed address in the beginning of ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt) . They cannot support any headers. Also, the first instruction in zImage header is to branch to the kernel start address. This is to support booting in situations where the zImage header need not be parsed. In case of Arm v8M, the first two entries in the reset vector should be "Initial value for the main stack pointer on reset" and "Start address for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30, Vector tables). In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table), the first entry is "SP_main. This is the reset value of the Main stack pointer.". Thus when v7M or v8M starts from reset, it expects to see these values at the default reset vector location. See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526) "On powerup or reset, the processor uses the entry at offset 0 as the initial value for SP_main..." Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2022-12-14 13:46:53 +01:00
if (CONFIG_ARM_ZIMAGE_HEADER)
zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors zimage_header.ld)
zephyr_linker_sources(ROM_START SORT_KEY 0x1vectors vector_table.ld)
zephyr_linker_sources(ROM_START SORT_KEY 0x2vectors cortex_m/vector_table_pad.ld)
else()
extensions.cmake: Replace TEXT_START with ROM_START In zephyr_linker_sources(). This is done since the point of the location is to place things at given offsets. This can only be done consistenly if the linker code is placed into the _first_ section. All uses of TEXT_START are replaced with ROM_START. ROM_START is only supported in some arches, as some arches have several custom sections before text. These don't currently have ROM_START or TEXT_START available, but that could be added with a bit of refactoring in their linker script. No SORT_KEYs are changed. This also fixes an error introduced when TEXT_START was added, where TEXT_SECTION_OFFSET was applied to riscv's common linker.ld instead of to openisa_rv32m1's specific linker.ld. Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-01-17 14:36:19 +01:00
zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
arm: vector_table: Automatically place the IRQ vector table Instead of using a custom linker script, rely on the automatic placement of the IRQ vector table. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-22 10:44:59 +02:00
zephyr_linker_sources(ROM_START SORT_KEY 0x1vectors cortex_m/vector_table_pad.ld)
arch: arm: aarch32: Add ability to generate zImage header The image header is compatible for zImage(32) protocol. Offset Value Description 0x24 0x016F2818 Magic number to identify ARM Linux zImage 0x28 start address The address the zImage starts at 0x2C end address The address the zImage ends at As Zephyr can be built with a fixed load address, Xen/Uboot can read the image header and decide where to copy the Zephyr image. Also, it is to be noted that for AArch32 A/R, the vector table should be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815, G8.2.168, VBAR, Vector Base Address Register :- Bits[4:0] = RES0. For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table Offset Register), Bits [6:0] = RES0. As zImage header occupies 0x30 bytes, thus it is necessary to align the vector table base address to 0x80 (which satisfies both VBAR and VTOR requirements). Also, it is to be noted that not all the AArch32 M class have VTOR, thus ARM_ZIMAGE_HEADER header depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR. The reason being the processors which does not have VBAR or VTOR, needs to have exception vector table at a fixed address in the beginning of ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt) . They cannot support any headers. Also, the first instruction in zImage header is to branch to the kernel start address. This is to support booting in situations where the zImage header need not be parsed. In case of Arm v8M, the first two entries in the reset vector should be "Initial value for the main stack pointer on reset" and "Start address for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30, Vector tables). In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table), the first entry is "SP_main. This is the reset value of the Main stack pointer.". Thus when v7M or v8M starts from reset, it expects to see these values at the default reset vector location. See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526) "On powerup or reset, the processor uses the entry at offset 0 as the initial value for SP_main..." Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2022-12-14 13:46:53 +01:00
endif()
arch: arm: Update to support local ISR declaration This commit updates the arm and arm64 architecture files to support the new ISR handlers creation parser. Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
2023-12-19 16:54:18 +01:00
if(CONFIG_GEN_SW_ISR_TABLE)
if(CONFIG_DYNAMIC_INTERRUPTS)
zephyr_linker_sources(RWDATA swi_tables.ld)
else()
zephyr_linker_sources(RODATA swi_tables.ld)
endif()
endif()
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