zephyr/soc/lowrisc/opentitan/Kconfig.defconfig

# Copyright (c) 2023 Rivos Inc.
# SPDX-License-Identifier: Apache-2.0

if SOC_OPENTITAN

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default 1000000

config RISCV_SOC_INTERRUPT_INIT
	default y

config RISCV_GP
	default y

config 2ND_LVL_ISR_TBL_OFFSET
	default 32

config 2ND_LVL_INTR_00_OFFSET
	default 11

config NUM_IRQS
	default 256

endif # SOC_OPENTITAN
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com> 2023-01-14 00:18:32 +01:00			`# Copyright (c) 2023 Rivos Inc.`
			`# SPDX-License-Identifier: Apache-2.0`

soc: riscv: opentitan: reorganize SoC folder Remove from riscv-privileged, and create a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2024-01-03 17:30:23 +01:00			`if SOC_OPENTITAN`
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com> 2023-01-14 00:18:32 +01:00
			`config SYS_CLOCK_HW_CYCLES_PER_SEC`
			`default 1000000`

			`config RISCV_SOC_INTERRUPT_INIT`
			`default y`

			`config RISCV_GP`
			`default y`

			`config 2ND_LVL_ISR_TBL_OFFSET`
			`default 32`

soc: riscv: riscv-privilege: opentitan: Fix PLIC interrupts 1. Fixes the number of interrupts in OpenTitan by default. This should be 32 + 185 = 217 IRQs, as there are 185 configurable registers, including interrupt 0. 2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a PLIC interrupt on IRQ 11. Signed-off-by: Tyler Ng <tkng@rivosinc.com> 2023-04-25 22:53:22 +02:00			`config 2ND_LVL_INTR_00_OFFSET`
			`default 11`

soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com> 2023-01-14 00:18:32 +01:00			`config NUM_IRQS`
soc/riscv/opentitan: Kconfig.defconfig.series: Set NUM_IRQS to 256 The OpenTitan PLIC has support for up to 255 interrupt vectors, so set it to that. Previously was set to number of IRQs used. Signed-off-by: Tyler Ng <tkng@rivosinc.com> 2024-01-19 17:48:41 +01:00			`default 256`
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com> 2023-01-14 00:18:32 +01:00
soc: riscv: opentitan: reorganize SoC folder Remove from riscv-privileged, and create a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2024-01-03 17:30:23 +01:00			`endif # SOC_OPENTITAN`