2015-11-17 23:08:45 +01:00
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/*
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* Copyright (c) 2015 Intel corporation
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2015-11-17 23:08:45 +01:00
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*/
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/**
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* @file Software interrupts utility code - ARM implementation
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*/
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2022-05-06 10:49:15 +02:00
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#include <zephyr/kernel.h>
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#include <zephyr/irq_offload.h>
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2015-11-17 23:08:45 +01:00
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2017-04-19 21:53:48 +02:00
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volatile irq_offload_routine_t offload_routine;
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2020-07-10 10:57:23 +02:00
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static const void *offload_param;
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2015-11-17 23:08:45 +01:00
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2019-09-30 21:31:07 +02:00
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/* Called by z_arm_svc */
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2019-03-14 16:20:46 +01:00
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void z_irq_do_offload(void)
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2015-11-17 23:08:45 +01:00
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{
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offload_routine(offload_param);
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}
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2020-07-10 10:57:23 +02:00
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void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
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2015-11-17 23:08:45 +01:00
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{
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2018-02-06 23:47:58 +01:00
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && defined(CONFIG_ASSERT)
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2019-02-07 10:05:30 +01:00
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/* ARMv6-M/ARMv8-M Baseline HardFault if you make a SVC call with
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* interrupts locked.
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2017-06-01 22:36:44 +02:00
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*/
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unsigned int key;
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2015-11-17 23:08:45 +01:00
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2017-06-01 22:36:44 +02:00
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__asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory");
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2019-03-27 02:57:45 +01:00
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__ASSERT(key == 0U, "irq_offload called with interrupts locked\n");
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2018-02-06 23:47:58 +01:00
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */
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2017-06-01 22:36:44 +02:00
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k_sched_lock();
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2015-11-17 23:08:45 +01:00
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offload_routine = routine;
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offload_param = parameter;
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2017-04-19 21:53:48 +02:00
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__asm__ volatile ("svc %[id]"
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:
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: [id] "i" (_SVC_CALL_IRQ_OFFLOAD)
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: "memory");
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offload_routine = NULL;
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2017-06-01 22:36:44 +02:00
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k_sched_unlock();
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2015-11-17 23:08:45 +01:00
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}
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