drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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description: |
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QSPI NOR flash supporting the JEDEC CFI interface.
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compatible: "nordic,qspi-nor"
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include: [base.yaml, "jedec,spi-nor-common.yaml"]
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on-bus: qspi
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properties:
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reg:
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required: true
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2020-06-27 16:57:27 +02:00
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jedec-id:
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required: true
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size:
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2022-01-07 13:09:18 +01:00
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type: int
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description: |
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The size in bits. Set this or size-in-bytes, but not both.
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size-in-bytes:
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type: int
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description: |
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The size in bytes. Set this or size, but not both.
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2020-06-27 16:57:27 +02:00
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2020-12-29 18:48:39 +01:00
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# Match original driver NORDIC_QSPI_NOR_QE_BIT Kconfig default.
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quad-enable-requirements:
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default: "S1B6"
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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readoc:
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type: string
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enum:
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2020-10-20 17:18:38 +02:00
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- "fastread" # Single data line SPI, FAST_READ (0x0B)
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2020-01-30 16:21:22 +01:00
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- "read2o" # Dual data line SPI, READ2O (0x3B)
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- "read2io" # Dual data line SPI, READ2IO (0xBB)
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- "read4o" # Quad data line SPI, READ4O (0x6B)
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- "read4io" # Quad data line SPI, READ4IO (0xEB)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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description: |
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Specify the number of data lines and opcode used for reading.
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If not provided fastread will be selected.
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writeoc:
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type: string
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enum:
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2020-01-30 16:21:22 +01:00
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- "pp" # Single data line SPI, PP (0x02)
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- "pp2o" # Dual data line SPI, PP2O (0xA2)
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2021-07-17 02:00:09 +02:00
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- "pp4o" # Quad data line SPI, PP4O (0x32)
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2020-01-30 16:21:22 +01:00
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- "pp4io" # Quad data line SPI, PP4IO (0x38)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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description: |
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2020-05-15 23:36:40 +02:00
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Specify the number of data lines and opcode used for writing.
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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If not provided pp will be selected.
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address-size-32:
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type: boolean
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description: |
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Set to indicate that 32-bit addressing is to be used.
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If not specified 24-bit addressing will be used.
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ppsize-512:
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type: boolean
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description: |
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Set to indicate that the write opcode operates on 512-byte pages.
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If not specified the write opcode operates on 256-byte pages.
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sck-delay:
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type: int
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default: 0
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description: |
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Number of clock cycles CSn must be asserted before it can go low
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again, specified in nanoseconds.
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2021-07-03 01:02:25 +02:00
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rx-delay:
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type: int
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description: |
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Number of clock cycles from the rising edge of the SPI clock
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until the input serial data is sampled.
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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cpha:
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type: boolean
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description: |
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Set to indicate phase starts with asserted half-phase (CPHA=1).
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For this driver using this property requires also using cpol.
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cpol:
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type: boolean
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description: |
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Set to indicate clock leading edge is falling (CPOL=1).
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For this driver using this property requires also using cpha.
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sck-frequency:
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type: int
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required: true
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description: |
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Maximum clock speed supported by the device, in Hz.
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