2016-01-14 14:48:12 +01:00
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/* spi_dw.h - Designware SPI driver private definitions */
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2015-11-22 03:28:21 +01:00
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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2016-01-14 14:48:12 +01:00
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#ifndef __SPI_DW_H__
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#define __SPI_DW_H__
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2015-11-22 03:28:21 +01:00
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#include <spi.h>
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2016-01-22 18:38:49 +01:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2016-01-08 09:46:14 +01:00
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typedef void (*spi_dw_config_t)(void);
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2015-11-22 03:28:21 +01:00
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/* Private structures */
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struct spi_dw_config {
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uint32_t regs;
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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void *clock_data;
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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2016-01-18 17:16:24 +01:00
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#ifdef CONFIG_SPI_DW_CS_GPIO
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char *cs_gpio_name;
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uint32_t cs_gpio_pin;
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#endif /* CONFIG_SPI_DW_CS_GPIO */
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2015-11-22 03:28:21 +01:00
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spi_dw_config_t config_func;
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};
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struct spi_dw_data {
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2015-12-08 13:30:41 +01:00
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device_sync_call_t sync;
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2016-01-15 10:11:24 +01:00
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uint32_t error:1;
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uint32_t dfs:3; /* dfs in bytes: 1,2 or 4 */
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uint32_t slave:17; /* up 16 slaves */
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uint32_t fifo_diff:9; /* cannot be bigger than FIFO depth */
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 20:55:09 +02:00
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uint32_t last_tx:1;
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uint32_t _unused:1;
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2015-11-22 03:28:21 +01:00
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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struct device *clock;
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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2016-01-18 17:16:24 +01:00
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#ifdef CONFIG_SPI_DW_CS_GPIO
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struct device *cs_gpio_port;
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#endif /* CONFIG_SPI_DW_CS_GPIO */
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2016-03-04 08:07:53 +01:00
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const uint8_t *tx_buf;
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2015-11-22 03:28:21 +01:00
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uint32_t tx_buf_len;
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uint8_t *rx_buf;
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uint32_t rx_buf_len;
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};
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spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 14:43:52 +01:00
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/* Helper macros */
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#ifdef CONFIG_SPI_DW_ARC_AUX_REGS
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#define _REG_READ(__sz) sys_in##__sz
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#define _REG_WRITE(__sz) sys_out##__sz
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#define _REG_SET_BIT sys_io_set_bit
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#define _REG_CLEAR_BIT sys_io_clear_bit
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#define _REG_TEST_BIT sys_io_test_bit
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#else
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#define _REG_READ(__sz) sys_read##__sz
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#define _REG_WRITE(__sz) sys_write##__sz
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#define _REG_SET_BIT sys_set_bit
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#define _REG_CLEAR_BIT sys_clear_bit
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#define _REG_TEST_BIT sys_test_bit
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#endif /* CONFIG_SPI_DW_ARC_AUX_REGS */
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#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
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static inline uint32_t read_##__reg(uint32_t addr) \
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{ \
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return _REG_READ(__sz)(addr + __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
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static inline void write_##__reg(uint32_t data, uint32_t addr) \
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{ \
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_REG_WRITE(__sz)(data, addr + __off); \
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}
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#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void set_bit_##__reg_bit(uint32_t addr) \
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{ \
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_REG_SET_BIT(addr + __reg_off, __bit); \
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}
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#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void clear_bit_##__reg_bit(uint32_t addr) \
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{ \
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_REG_CLEAR_BIT(addr + __reg_off, __bit); \
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}
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#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline int test_bit_##__reg_bit(uint32_t addr) \
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{ \
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return _REG_TEST_BIT(addr + __reg_off, __bit); \
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}
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/* Common registers settings, bits etc... */
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2015-11-22 03:28:21 +01:00
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/* CTRLR0 settings */
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spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 14:43:52 +01:00
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#define DW_SPI_CTRLR0_SCPH_BIT (6)
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#define DW_SPI_CTRLR0_SCPOL_BIT (7)
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#define DW_SPI_CTRLR0_SRL_BIT (11)
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#define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT)
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#define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
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#define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
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2016-01-14 16:04:28 +01:00
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#define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1)
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#define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16)
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spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 14:43:52 +01:00
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2016-01-14 16:04:28 +01:00
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#ifdef CONFIG_ARC
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#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_16
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#else
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#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_32
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#endif
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2015-11-22 03:28:21 +01:00
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2016-01-15 10:11:24 +01:00
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/* 0x38 represents the bits 8,16 and 32. Knowing that 24 is bits 8 and 16
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* These are the bits were when you divide by 8, you keep the result as it is.
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* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
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* since on such division it takes only the result above 0
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*/
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#define SPI_DFS_TO_BYTES(__bpw) (((__bpw) & ~0x38) ? \
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(((__bpw) / 8) + 1) : \
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((__bpw) / 8))
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2015-12-19 00:26:42 +01:00
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2015-11-22 03:28:21 +01:00
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/* SSIENR bits */
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#define DW_SPI_SSIENR_SSIEN_BIT (0)
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/* SR bits and values */
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#define DW_SPI_SR_BUSY_BIT (0)
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#define DW_SPI_SR_TFNF_BIT (1)
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#define DW_SPI_SR_RFNE_BIT (3)
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2016-01-14 17:45:05 +01:00
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/* IMR bits (ISR valid as well) */
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2015-11-22 03:28:21 +01:00
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#define DW_SPI_IMR_TXEIM_BIT (0)
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#define DW_SPI_IMR_TXOIM_BIT (1)
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#define DW_SPI_IMR_RXUIM_BIT (2)
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#define DW_SPI_IMR_RXOIM_BIT (3)
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#define DW_SPI_IMR_RXFIM_BIT (4)
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#define DW_SPI_IMR_MSTIM_BIT (5)
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2016-01-14 17:45:05 +01:00
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/* IMR values */
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spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 14:43:52 +01:00
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#define DW_SPI_IMR_TXEIM BIT(DW_SPI_IMR_TXEIM_BIT)
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#define DW_SPI_IMR_TXOIM BIT(DW_SPI_IMR_TXOIM_BIT)
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#define DW_SPI_IMR_RXUIM BIT(DW_SPI_IMR_RXUIM_BIT)
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#define DW_SPI_IMR_RXOIM BIT(DW_SPI_IMR_RXOIM_BIT)
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#define DW_SPI_IMR_RXFIM BIT(DW_SPI_IMR_RXFIM_BIT)
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#define DW_SPI_IMR_MSTIM BIT(DW_SPI_IMR_MSTIM_BIT)
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2016-01-14 17:45:05 +01:00
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/* ISR values (same as IMR) */
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#define DW_SPI_ISR_TXEIS DW_SPI_IMR_TXEIM
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#define DW_SPI_ISR_TXOIS DW_SPI_IMR_TXOIM
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#define DW_SPI_ISR_RXUIS DW_SPI_IMR_RXUIM
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#define DW_SPI_ISR_RXOIS DW_SPI_IMR_RXOIM
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#define DW_SPI_ISR_RXFIS DW_SPI_IMR_RXFIM
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#define DW_SPI_ISR_MSTIS DW_SPI_IMR_MSTIM
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2015-11-22 03:28:21 +01:00
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/* Error interrupt */
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2016-01-14 17:45:05 +01:00
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#define DW_SPI_ISR_ERRORS_MASK (DW_SPI_ISR_TXOIS | \
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2015-11-22 03:28:21 +01:00
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DW_SPI_ISR_RXUIS | \
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DW_SPI_ISR_RXOIS | \
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DW_SPI_ISR_MSTIS)
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/* ICR Bit */
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#define DW_SPI_SR_ICR_BIT (0)
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/* Threshold defaults */
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2016-05-18 22:11:35 +02:00
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#define DW_SPI_FIFO_DEPTH CONFIG_SPI_DW_FIFO_DEPTH
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#define DW_SPI_TXFTLR_DFLT ((DW_SPI_FIFO_DEPTH*5)/8)
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#define DW_SPI_RXFTLR_DFLT ((DW_SPI_FIFO_DEPTH*5)/8)
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2015-11-22 03:28:21 +01:00
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/* Interrupt mask (IMR) */
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#define DW_SPI_IMR_MASK (0x0)
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2016-01-14 17:45:05 +01:00
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#define DW_SPI_IMR_UNMASK (DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM | \
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DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM)
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#define DW_SPI_IMR_MASK_TX (~(DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM))
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#define DW_SPI_IMR_MASK_RX (~(DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM))
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2015-11-22 03:28:21 +01:00
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spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 14:43:52 +01:00
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/*
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* Including the right register definition file
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* SoC SPECIFIC!
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*/
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#ifdef CONFIG_SOC_QUARK_SE_SS
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#include "spi_dw_quark_se_ss_regs.h"
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#else
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#include "spi_dw_regs.h"
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#endif
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/* GPIO used to emulate CS */
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#ifdef CONFIG_SPI_DW_CS_GPIO
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#include <gpio.h>
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static inline void _spi_config_cs(struct device *dev)
|
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{
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struct spi_dw_config *info = dev->config->config_info;
|
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struct spi_dw_data *spi = dev->driver_data;
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struct device *gpio;
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gpio = device_get_binding(info->cs_gpio_name);
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if (!gpio) {
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spi->cs_gpio_port = NULL;
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return;
|
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}
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gpio_pin_configure(gpio, info->cs_gpio_pin, GPIO_DIR_OUT);
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/* Default CS line to high (idling) */
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gpio_pin_write(gpio, info->cs_gpio_pin, 1);
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spi->cs_gpio_port = gpio;
|
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}
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static inline void _spi_control_cs(struct device *dev, int on)
|
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|
|
|
{
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|
struct spi_dw_config *info = dev->config->config_info;
|
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struct spi_dw_data *spi = dev->driver_data;
|
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if (spi->cs_gpio_port) {
|
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|
gpio_pin_write(spi->cs_gpio_port, info->cs_gpio_pin, !on);
|
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|
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}
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}
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|
#else
|
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|
|
#define _spi_control_cs(...)
|
|
|
|
|
#define _spi_config_cs(...)
|
|
|
|
|
#endif /* CONFIG_SPI_DW_CS_GPIO */
|
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|
/* Interrupt mask
|
|
|
|
|
* SoC SPECIFIC!
|
|
|
|
|
*/
|
|
|
|
|
#if defined(CONFIG_SOC_QUARK_SE) || defined(CONFIG_SOC_QUARK_SE_SS)
|
|
|
|
|
#ifdef CONFIG_ARC
|
|
|
|
|
#define _INT_UNMASK INT_ENABLE_ARC
|
|
|
|
|
#else
|
|
|
|
|
#define _INT_UNMASK INT_UNMASK_IA
|
|
|
|
|
#endif
|
|
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|
|
|
|
|
#define _spi_int_unmask(__mask) \
|
|
|
|
|
sys_write32(sys_read32(__mask) & _INT_UNMASK, __mask)
|
|
|
|
|
#else
|
|
|
|
|
#define _spi_int_unmask(...)
|
|
|
|
|
#endif /* CONFIG_SOC_QUARK_SE || CONFIG_SOC_QUARK_SE_SS */
|
|
|
|
|
|
|
|
|
|
/* Based on those macros above, here are common helpers for some registers */
|
|
|
|
|
DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
|
|
|
|
|
DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32)
|
|
|
|
|
DEFINE_MM_REG_READ(rxflr, DW_SPI_REG_RXFLR, 32)
|
|
|
|
|
DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
|
|
|
|
|
DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)
|
|
|
|
|
|
|
|
|
|
DEFINE_SET_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
|
|
|
|
|
DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
|
|
|
|
|
DEFINE_TEST_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
|
|
|
|
|
DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
|
|
|
|
|
|
2016-01-22 18:38:49 +01:00
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2016-01-14 14:48:12 +01:00
|
|
|
#endif /* __SPI_DW_H__ */
|
2016-01-22 18:38:49 +01:00
|
|
|
|