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boards: hifive_unmatched: update ram size

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Update ram size to 16GB.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
This commit is contained in:
Franciszek Zdobylak 2023-04-06 11:45:15 +02:00 committed by Carles Cufí
parent 0c0690e654
commit 00b6f4a8ce
2 changed files with 22 additions and 22 deletions
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4
boards/riscv/hifive_unmatched/hifive_unmatched.dts
View file

@ -17,7 +17,7 @@
ram0: ram0@80000000 {
compatible = "memory";
reg = <0x80000000 0xf0000000>;
reg = <0x0 0x80000000 0x4 0x00000000>;
reg-names = "mem";
};
};
@ -29,7 +29,7 @@
/* disabled (used by Flash ROM by default) */
&spi0 {
reg = <0x10040000 0x1000 0x20000000 0x2000000>;
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x2000000>;
flash0: flash@0 {
compatible = "issi,is25wp256d", "jedec,spi-nor";
status = "disabled";

40
dts/riscv/sifive/riscv64-fu740.dtsi
View file

@ -8,8 +8,8 @@
#include <freq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
model = "sifive,FU740";
@ -48,38 +48,38 @@
};
soc {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
modeselect: rom@1000 {
compatible = "sifive,modeselect0";
reg = <0x1000 0x1000>;
reg = <0x0 0x1000 0x0 0x1000>;
reg-names = "mem";
};
maskrom: rom@10000 {
compatible = "sifive,maskrom0";
reg = <0x10000 0x8000>;
reg = <0x0 0x10000 0x0 0x8000>;
reg-names = "mem";
};
dtim: dtim@1000000 {
compatible = "sifive,dtim0";
reg = <0x1000000 0x2000>;
reg = <0x0 0x1000000 0x0 0x2000>;
reg-names = "mem";
};
clint: clint@2000000 {
compatible = "sifive,clint0";
interrupts-extended = <&hlic 3 &hlic 7>;
reg = <0x2000000 0x10000>;
reg = <0x0 0x2000000 0x0 0x10000>;
};
l2lim: l2lim@8000000 {
compatible = "sifive,l2lim0";
reg = <0x8000000 0x200000>;
reg = <0x0 0x8000000 0x0 0x200000>;
reg-names = "mem";
};
@ -90,9 +90,9 @@
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0x0c000000 0x00002000
0x0c002000 0x001fe000
0x0c200000 0x03e00000>;
reg = <0x0 0x0c000000 0x0 0x00002000
0x0 0x0c002000 0x0 0x001fe000
0x0 0x0c200000 0x0 0x03e00000>;
reg-names = "prio", "irq_en", "reg";
riscv,max-priority = <7>;
riscv,ndev = <52>;
@ -102,7 +102,7 @@
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <39 1>;
reg = <0x10010000 0x1000>;
reg = <0x0 0x10010000 0x0 0x1000>;
reg-names = "control";
status = "disabled";
};
@ -111,7 +111,7 @@
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <40 1>;
reg = <0x10011000 0x1000>;
reg = <0x0 0x10011000 0x0 0x1000>;
reg-names = "control";
status = "disabled";
};
@ -120,7 +120,7 @@
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <41 1>;
reg = <0x10040000 0x1000 0x20000000 0x10000000>;
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
reg-names = "control", "mem";
status = "disabled";
#address-cells = <1>;
@ -131,7 +131,7 @@
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <42 1>;
reg = <0x10041000 0x1000>;
reg = <0x0 0x10041000 0x0 0x1000>;
reg-names = "control";
status = "disabled";
#address-cells = <1>;
@ -142,7 +142,7 @@
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <43 1>;
reg = <0x10050000 0x1000>;
reg = <0x0 0x10050000 0x0 0x1000>;
reg-names = "control";
status = "disabled";
#address-cells = <1>;
@ -150,9 +150,9 @@
};
dmc: dmc@100b0000 {
compatible = "sifive,fu740-c000-ddr";
reg = <0x100b0000 0x0800
0x100b2000 0x2000
0x100b8000 0x1000>;
reg = <0x0 0x100b0000 0x0 0x0800
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>;
status = "disabled";
};
};