diff --git a/drivers/reset/CMakeLists.txt b/drivers/reset/CMakeLists.txt index 36c68367d3..f27f31f683 100644 --- a/drivers/reset/CMakeLists.txt +++ b/drivers/reset/CMakeLists.txt @@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_AST10X0 reset_ast10x0.c) zephyr_library_sources_ifdef(CONFIG_RESET_STM32 reset_stm32.c) zephyr_library_sources_ifdef(CONFIG_RESET_NUMAKER reset_numaker.c) zephyr_library_sources_ifdef(CONFIG_RESET_INTEL_SOCFPGA reset_intel_socfpga.c) +zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index f940583c97..1d361aa8e2 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -33,5 +33,6 @@ rsource "Kconfig.aspeed" rsource "Kconfig.stm32" rsource "Kconfig.numaker" rsource "Kconfig.intel_socfpga" +rsource "Kconfig.npcx" endif # RESET diff --git a/drivers/reset/Kconfig.npcx b/drivers/reset/Kconfig.npcx new file mode 100644 index 0000000000..1ce6d27fec --- /dev/null +++ b/drivers/reset/Kconfig.npcx @@ -0,0 +1,11 @@ +# NPCX reset controller driver configuration options + +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config RESET_NPCX + bool "Nuvoton NPCX embedded controller (EC) reset controller driver" + default y + depends on DT_HAS_NUVOTON_NPCX_RST_ENABLED + help + This option enables the reset controller driver for Nuvoton NPCX MCUs. diff --git a/drivers/reset/reset_npcx.c b/drivers/reset/reset_npcx.c new file mode 100644 index 0000000000..af9cac37f0 --- /dev/null +++ b/drivers/reset/reset_npcx.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nuvoton_npcx_rst + +#include +#include + +#if defined(CONFIG_SOC_SERIES_NPCX7) +#include +#elif defined(CONFIG_SOC_SERIES_NPCX9) +#include +#elif defined(CONFIG_SOC_SERIES_NPCX4) +#include +#endif + +#include +LOG_MODULE_REGISTER(rst_npcx); + +#define NPCX_RESET_CTL_REG_BYTE_SIZE 4 +#define NPCX_RESET_CTL_REG_OFFSET(id) ((id) >> (NPCX_RESET_CTL_REG_BYTE_SIZE + 1)) +#define NPCX_RESET_CTL_REG_BIT(id) (((id) & ((1 << (NPCX_RESET_CTL_REG_BYTE_SIZE + 1)) - 1))) + +#define NPCX_SWRST_TRG_WORD_START 0xC183 +#define NPCX_SWRST_TRG_WORD_CLEAR 0x0 +#define NPCX_SWRST_TRG_WORD_DONE 0xFFFF +#define NPCX_SWRST_DONE_TIMEOUT_US 100 + +struct reset_npcx_dev_config { + struct swrst_reg *reg_base; +}; + +static int reset_npcx_line_toggle(const struct device *dev, uint32_t id) +{ + const struct reset_npcx_dev_config *const config = dev->config; + struct swrst_reg *const reg = config->reg_base; + unsigned int key; + uint8_t reg_offset; + uint8_t reg_bit; + int ret = 0; + + if (!IN_RANGE(id, NPCX_RESET_ID_START, NPCX_RESET_ID_END)) { + LOG_ERR("Invalid Reset ID"); + return -EINVAL; + } + reg_offset = NPCX_RESET_CTL_REG_OFFSET(id); + reg_bit = NPCX_RESET_CTL_REG_BIT(id); + + key = irq_lock(); + + reg->SWRST_CTL[reg_offset] |= BIT(reg_bit); + reg->SWRST_TRG = NPCX_SWRST_TRG_WORD_CLEAR; + reg->SWRST_TRG = NPCX_SWRST_TRG_WORD_START; + + if (!WAIT_FOR((reg->SWRST_TRG == NPCX_SWRST_TRG_WORD_DONE), NPCX_SWRST_DONE_TIMEOUT_US, + NULL)) { + LOG_ERR("Reset trig timeout"); + ret = -EBUSY; + } + + irq_unlock(key); + + return ret; +} + +static const struct reset_driver_api reset_npcx_driver_api = { + .line_toggle = reset_npcx_line_toggle, +}; + +static const struct reset_npcx_dev_config reset_npcx_config = { + .reg_base = (struct swrst_reg *)DT_INST_REG_ADDR(0), +}; + +DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_npcx_config, PRE_KERNEL_1, + CONFIG_RESET_INIT_PRIORITY, &reset_npcx_driver_api); diff --git a/dts/arm/nuvoton/npcx/npcx4.dtsi b/dts/arm/nuvoton/npcx/npcx4.dtsi index 004ca5332a..9070b4a712 100644 --- a/dts/arm/nuvoton/npcx/npcx4.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4.dtsi @@ -317,6 +317,13 @@ status = "disabled"; }; }; + + rctl: reset-controller@400c3100 { + compatible = "nuvoton,npcx-rst"; + reg = <0x400c3100 0x14>; + #reset-cells = <1>; + status = "disabled"; + }; }; soc-if { diff --git a/dts/arm/nuvoton/npcx/npcx7.dtsi b/dts/arm/nuvoton/npcx/npcx7.dtsi index be00312759..fb4001c177 100644 --- a/dts/arm/nuvoton/npcx/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7.dtsi @@ -260,6 +260,13 @@ rx-plsize = <64>; tx-plsize = <16>; }; + + rctl: reset-controller@400c3100 { + compatible = "nuvoton,npcx-rst"; + reg = <0x400c3100 0x10>; + #reset-cells = <1>; + status = "disabled"; + }; }; soc-id { diff --git a/dts/arm/nuvoton/npcx/npcx9.dtsi b/dts/arm/nuvoton/npcx/npcx9.dtsi index e3004ab879..4a49e2c270 100644 --- a/dts/arm/nuvoton/npcx/npcx9.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9.dtsi @@ -288,6 +288,13 @@ rx-plsize = <64>; tx-plsize = <16>; }; + + rctl: reset-controller@400c3100 { + compatible = "nuvoton,npcx-rst"; + reg = <0x400c3100 0x14>; + #reset-cells = <1>; + status = "disabled"; + }; }; soc-id { diff --git a/dts/bindings/reset/nuvoton,npcx-rst.yaml b/dts/bindings/reset/nuvoton,npcx-rst.yaml new file mode 100644 index 0000000000..3efceb3ae9 --- /dev/null +++ b/dts/bindings/reset/nuvoton,npcx-rst.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: NPCX Reset Controller + +compatible: "nuvoton,npcx-rst" + +include: [reset-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#reset-cells": + const: 1 + +reset-cells: +- id diff --git a/include/zephyr/dt-bindings/reset/npcx4_reset.h b/include/zephyr/dt-bindings/reset/npcx4_reset.h new file mode 100644 index 0000000000..46793b66ea --- /dev/null +++ b/include/zephyr/dt-bindings/reset/npcx4_reset.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H + +#define NPCX_RESET_SWRST_CTL1_OFFSET 0 +#define NPCX_RESET_SWRST_CTL2_OFFSET 32 +#define NPCX_RESET_SWRST_CTL3_OFFSET 64 +#define NPCX_RESET_SWRST_CTL4_OFFSET 96 + +#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) +#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) +#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) +#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) +#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) +#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) +#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) +#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) +#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) +#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) +#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) +#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) +#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) +#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) +#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) +#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) +#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) +#define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) +#define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) +#define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) +#define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) +#define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) +#define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) +#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) +#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) +#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) +#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) +#define NPCX_RESET_GDMA1 (NPCX_RESET_SWRST_CTL1_OFFSET + 29) +#define NPCX_RESET_GDMA2 (NPCX_RESET_SWRST_CTL1_OFFSET + 30) + +#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) +#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) +#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) +#define NPCX_RESET_ADCE (NPCX_RESET_SWRST_CTL2_OFFSET + 4) +#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) +#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) +#define NPCX_RESET_ADCI (NPCX_RESET_SWRST_CTL2_OFFSET + 7) +#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) +#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) +#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) +#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) +#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) +#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) +#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) +#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) +#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) +#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) +#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) +#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) +#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) +#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) +#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) +#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) +#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) +#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) +#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) +#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) +#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) +#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) +#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) +#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) + +#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) +#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) +#define NPCX_RESET_I3C_1 (NPCX_RESET_SWRST_CTL3_OFFSET + 4) +#define NPCX_RESET_I3C_2 (NPCX_RESET_SWRST_CTL3_OFFSET + 5) +#define NPCX_RESET_I3C_3 (NPCX_RESET_SWRST_CTL3_OFFSET + 6) +#define NPCX_RESET_I3C_RD (NPCX_RESET_SWRST_CTL3_OFFSET + 7) +#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) +#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) +#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) +#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) +#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) +#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) +#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) +#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) +#define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18) +#define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19) +#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) +#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) +#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) +#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) +#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) +#define NPCX_RESET_SHA_2B (NPCX_RESET_SWRST_CTL3_OFFSET + 26) +#define NPCX_RESET_SHA_2A (NPCX_RESET_SWRST_CTL3_OFFSET + 29) + +#define NPCX_RESET_MDC (NPCX_RESET_SWRST_CTL4_OFFSET + 15) +#define NPCX_RESET_FIU0 (NPCX_RESET_SWRST_CTL4_OFFSET + 16) +#define NPCX_RESET_FIU1 (NPCX_RESET_SWRST_CTL4_OFFSET + 17) +#define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24) +#define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25) +#define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26) +#define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27) +#define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28) +#define NPCX_RESET_MDMA6 (NPCX_RESET_SWRST_CTL4_OFFSET + 29) +#define NPCX_RESET_MDMA7 (NPCX_RESET_SWRST_CTL4_OFFSET + 30) + +#define NPCX_RESET_ID_START NPCX_RESET_GPIO0 +#define NPCX_RESET_ID_END NPCX_RESET_MDMA7 +#endif diff --git a/include/zephyr/dt-bindings/reset/npcx7_reset.h b/include/zephyr/dt-bindings/reset/npcx7_reset.h new file mode 100644 index 0000000000..b9df548297 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/npcx7_reset.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H + +#define NPCX_RESET_SWRST_CTL1_OFFSET 0 +#define NPCX_RESET_SWRST_CTL2_OFFSET 32 +#define NPCX_RESET_SWRST_CTL3_OFFSET 64 + +#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) +#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) +#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) +#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) +#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) +#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) +#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) +#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) +#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) +#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) +#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) +#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) +#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) +#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) +#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) +#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) +#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) +#define NPCX_RESET_ITIM16_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) +#define NPCX_RESET_ITIM16_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) +#define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) +#define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) +#define NPCX_RESET_ITIM16_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) +#define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) +#define NPCX_RESET_ITIM32 (NPCX_RESET_SWRST_CTL1_OFFSET + 24) +#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) +#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) +#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) +#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) +#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29) +#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30) + +#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) +#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) +#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) +#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) +#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) +#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7) +#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) +#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) +#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) +#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) +#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) +#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) +#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) +#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) +#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) +#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) +#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) +#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) +#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) +#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) +#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) +#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) +#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) +#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) +#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) +#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) +#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) +#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) +#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) +#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) + +#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) +#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) +#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) +#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) +#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) +#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) +#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) +#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) +#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) +#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) +#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) +#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) +#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) +#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) +#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) + +#define NPCX_RESET_ID_START NPCX_RESET_GPIO0 +#define NPCX_RESET_ID_END NPCX_RESET_BBRAM +#endif diff --git a/include/zephyr/dt-bindings/reset/npcx9_reset.h b/include/zephyr/dt-bindings/reset/npcx9_reset.h new file mode 100644 index 0000000000..c8032bddd3 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/npcx9_reset.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H + +#define NPCX_RESET_SWRST_CTL1_OFFSET 0 +#define NPCX_RESET_SWRST_CTL2_OFFSET 32 +#define NPCX_RESET_SWRST_CTL3_OFFSET 64 +#define NPCX_RESET_SWRST_CTL4_OFFSET 96 + +#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) +#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) +#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) +#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) +#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) +#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) +#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) +#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) +#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) +#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) +#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) +#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) +#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) +#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) +#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) +#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) +#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) +#define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) +#define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) +#define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) +#define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) +#define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) +#define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) +#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) +#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) +#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) +#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) +#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29) +#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30) + +#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) +#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) +#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) +#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) +#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) +#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7) +#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) +#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) +#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) +#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) +#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) +#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) +#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) +#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) +#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) +#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) +#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) +#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) +#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) +#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) +#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) +#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) +#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) +#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) +#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) +#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) +#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) +#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) +#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) +#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) + +#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) +#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) +#define NPCX_RESET_I3C (NPCX_RESET_SWRST_CTL3_OFFSET + 5) +#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) +#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) +#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) +#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) +#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) +#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) +#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) +#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) +#define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18) +#define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19) +#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) +#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) +#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) +#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) +#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) +#define NPCX_RESET_SHA (NPCX_RESET_SWRST_CTL3_OFFSET + 29) + +#define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24) +#define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25) +#define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26) +#define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27) +#define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28) + +#define NPCX_RESET_ID_START NPCX_RESET_GPIO0 +#define NPCX_RESET_ID_END NPCX_RESET_MDMA5 +#endif diff --git a/soc/nuvoton/npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h index f13dfd507f..e8d4761074 100644 --- a/soc/nuvoton/npcx/common/reg/reg_def.h +++ b/soc/nuvoton/npcx/common/reg/reg_def.h @@ -1756,4 +1756,12 @@ struct spip_reg { #define NPCX_SPIP_STAT_BSY 0 #define NPCX_SPIP_STAT_RBF 1 +/* Software-triggered Pheripheral Reset Controller Register */ +struct swrst_reg { + /* 0x000: Software Reset Trigger */ + volatile uint16_t SWRST_TRG; + volatile uint8_t reserved1[2]; + volatile uint32_t SWRST_CTL[4]; +}; + #endif /* _NUVOTON_NPCX_REG_DEF_H */ diff --git a/soc/nuvoton/npcx/common/registers.c b/soc/nuvoton/npcx/common/registers.c index 8c4ed132b4..e12b3bc103 100644 --- a/soc/nuvoton/npcx/common/registers.c +++ b/soc/nuvoton/npcx/common/registers.c @@ -189,3 +189,11 @@ NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a); /* SPIP register structure check */ NPCX_REG_SIZE_CHECK(spip_reg, 0x006); NPCX_REG_OFFSET_CHECK(spip_reg, SPIP_CTL1, 0x002); + +/* SWRST register structure check */ +NPCX_REG_SIZE_CHECK(swrst_reg, 0x014); +NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_TRG, 0x000); +NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[0], 0x004); +NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[1], 0x008); +NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c); +NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);