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riscv: enable booting from non-zero indexed RISC-V hart

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RISC-V multi-hart systems that employ a heterogeneous core complex are
not guaranteed to have the smp capable harts starting with a unique id
of zero, matching Zephyr's sequential zero indexed cpu numbering scheme.

Add option, RV_BOOT_HART to choose the hart to boot from.
On reset, check the current hart equals RV_BOOT_HART: if so, boot first
core. else, loop in the boot secondary core and wait to be brought up.

For multi-hart systems that are not running a Zephyr mp or smp
application, park the non zephyr related harts in a wfi loop.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This commit is contained in:
Conor Paxton 2023-01-16 13:53:06 +00:00 committed by Fabio Baltieri
parent 20644536b9
commit 02391ed00d
2 changed files with 15 additions and 8 deletions
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8
arch/riscv/Kconfig
View file

@ -171,6 +171,14 @@ config GEN_IRQ_VECTOR_TABLE
config NUM_IRQS
int
config RV_BOOT_HART
int "Starting HART ID"
default 0
help
This option sets the starting HART ID for the SMP core.
For RISC-V systems such as MPFS and FU540 this would be set to 1 to
skip the E51 HART 0 as it is not usable in SMP configurations.
config RISCV_PMP
bool "RISC-V PMP Support"
select THREAD_STACK_INFO

15
arch/riscv/core/reset.S
View file

@ -39,14 +39,9 @@ SECTION_FUNC(reset, __reset)
*/
SECTION_FUNC(TEXT, __initialize)
csrr a0, mhartid
beqz a0, boot_first_core
li t0, CONFIG_MP_MAX_NUM_CPUS
blt a0, t0, boot_secondary_core
loop_unconfigured_cores:
wfi
j loop_unconfigured_cores
li t0, CONFIG_RV_BOOT_HART
beq a0, t0, boot_first_core
j boot_secondary_core
boot_first_core:
@ -112,3 +107,7 @@ boot_secondary_core:
#else
j loop_unconfigured_cores
#endif
loop_unconfigured_cores:
wfi
j loop_unconfigured_cores