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arch/x86: eliminate include/arch/x86/irq_controller.h

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The MVIC is no longer supported, and only the APIC-based interrupt
subsystem remains. Thus this layer of indirection is unnecessary.

This also corrects an oversight left over from the Jailhouse x2APIC
implementation affecting EOI delivery for direct ISRs only.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-06-28 13:06:37 -07:00 committed by Anas Nashif
parent 15dac5b6ab
commit 0325a3d972
9 changed files with 26 additions and 131 deletions
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2
arch/x86/core/ia32/fatal.c
View file

@ -17,7 +17,7 @@
#include <kernel.h>
#include <kernel_structs.h>
#include <sys/printk.h>
#include <arch/x86/irq_controller.h>
#include <drivers/interrupt_controller/sysapic.h>
#include <arch/x86/ia32/segmentation.h>
#include <exception.h>
#include <inttypes.h>

12
arch/x86/core/ia32/intstub.S
View file

@ -18,7 +18,7 @@
#include <arch/x86/ia32/asm.h>
#include <offsets_short.h>
#include <arch/cpu.h> /* _NANO_ERR_SPURIOUS_INT */
#include <arch/x86/irq_controller.h>
#include <drivers/interrupt_controller/sysapic.h>
/* exports (internal APIs) */
@ -210,8 +210,14 @@ alreadyOnIntStack:
cli /* disable interrupts again */
#endif
/* irq_controller.h interface */
_irq_controller_eoi_macro
#if defined(CONFIG_EOI_FORWARDING_BUG)
call z_lakemont_eoi
#elif defined(CONFIG_X2APIC)
call z_x2apic_eoi
#else /* xAPIC EOI */
xorl %eax, %eax
movl %eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
#endif
/* determine whether exiting from a nested interrupt */
movl $_kernel, %ecx

2
drivers/interrupt_controller/loapic_intr.c
View file

@ -295,7 +295,7 @@ void z_loapic_irq_disable(unsigned int irq)
* @return The vector of the interrupt that is currently being processed, or -1
* if no IRQ is being serviced.
*/
int __irq_controller_isr_vector_get(void)
int z_irq_controller_isr_vector_get(void)
{
int pReg, block;

2
drivers/interrupt_controller/system_apic.c
View file

@ -43,7 +43,7 @@
* @param flags interrupt flags
*
*/
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
void z_irq_controller_irq_config(unsigned int vector, unsigned int irq,
u32_t flags)
{
__ASSERT(irq <= HARDWARE_IRQ_LIMIT, "invalid irq line");

1
drivers/timer/loapic_timer.c
View file

@ -61,7 +61,6 @@
#include <linker/sections.h>
#include <sys_clock.h>
#include <drivers/timer/system_timer.h>
#include <arch/x86/irq_controller.h>
#include <power/power.h>
#include <device.h>
#include <kernel_structs.h>

4
include/arch/x86/ia32/arch.h
View file

@ -16,7 +16,7 @@
#include <irq.h>
#include "sys_io.h"
#include <arch/x86/irq_controller.h>
#include <drivers/interrupt_controller/sysapic.h>
#include <kernel_arch_thread.h>
#include <generated_dts_board.h>
#include <mmustructs.h>
@ -193,7 +193,7 @@ typedef struct s_isrList {
* @param priority_p Interrupt priority
* @param isr_p Interrupt service routine
* @param isr_param_p ISR parameter
* @param flags_p IRQ triggering options, as defined in irq_controller.h
* @param flags_p IRQ triggering options, as defined in sysapic.h
*
* @return The vector assigned to this interrupt
*/

93
include/arch/x86/irq_controller.h
View file

@ -1,93 +0,0 @@
/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Abstraction layer for x86 interrupt controllers
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_IRQ_CONTROLLER_H_
#define ZEPHYR_INCLUDE_ARCH_X86_IRQ_CONTROLLER_H_
#include <drivers/interrupt_controller/sysapic.h>
/* Triggering flags abstraction layer.
* If a particular set of triggers is not supported, leave undefined
*/
#define IRQ_TRIGGER_EDGE _IRQ_TRIGGER_EDGE
#define IRQ_TRIGGER_LEVEL _IRQ_TRIGGER_LEVEL
#define IRQ_POLARITY_HIGH _IRQ_POLARITY_HIGH
#define IRQ_POLARITY_LOW _IRQ_POLARITY_LOW
#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
/**
*
* @brief Program an interrupt
*
* This function sets the triggering options for an IRQ and also associates
* the IRQ with its vector in the IDT. This does not enable the interrupt
* line, it will be left masked.
*
* The flags parameter is limited to the IRQ_TRIGGER_* defines above. In
* addition, not all interrupt controllers support all flags.
*
* @param irq Virtualized IRQ
* @param vector Vector Number
* @param flags Interrupt flags
*
* @returns: N/A
*/
static inline void z_irq_controller_irq_config(unsigned int vector,
unsigned int irq, u32_t flags)
{
__irq_controller_irq_config(vector, irq, flags);
}
/**
* @brief Return the vector of the currently in-service ISR
*
* This function should be called in interrupt context.
* It is not expected for this function to reveal the identity of
* vectors triggered by a CPU exception or 'int' instruction.
*
* @return the vector of the interrupt that is currently being processed, or
* -1 if this can't be determined
*/
static inline int z_irq_controller_isr_vector_get(void)
{
return __irq_controller_isr_vector_get();
}
static inline void z_irq_controller_eoi(void)
{
__irq_controller_eoi();
}
#else /* _ASMLANGUAGE */
/**
* @brief Send EOI to the interrupt controller
*
* This macro is used by the core interrupt handling code. Interrupts
* will be locked when this gets called and will not be unlocked until
* 'iret' has been issued.
*
* This macro is used in exactly one spot in intStub.S, in _IntExitWithEoi.
* At the time this is called, implementations are free to use the caller-
* saved registers eax, edx, ecx for their own purposes with impunity but
* need to preserve all callee-saved registers.
*/
.macro _irq_controller_eoi_macro
__irq_controller_eoi_macro
.endm
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_IRQ_CONTROLLER_H_ */

39
include/drivers/interrupt_controller/sysapic.h
View file

@ -9,11 +9,11 @@
#include <drivers/interrupt_controller/loapic.h>
#define _IRQ_TRIGGER_EDGE IOAPIC_EDGE
#define _IRQ_TRIGGER_LEVEL IOAPIC_LEVEL
#define IRQ_TRIGGER_EDGE IOAPIC_EDGE
#define IRQ_TRIGGER_LEVEL IOAPIC_LEVEL
#define _IRQ_POLARITY_HIGH IOAPIC_HIGH
#define _IRQ_POLARITY_LOW IOAPIC_LOW
#define IRQ_POLARITY_HIGH IOAPIC_HIGH
#define IRQ_POLARITY_LOW IOAPIC_LOW
#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
@ -21,43 +21,26 @@
#define LOAPIC_IRQ_BASE CONFIG_IOAPIC_NUM_RTES
#define LOAPIC_IRQ_COUNT 6 /* Default to LOAPIC_TIMER to LOAPIC_ERROR */
/* irq_controller.h interface */
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
void z_irq_controller_irq_config(unsigned int vector, unsigned int irq,
u32_t flags);
int __irq_controller_isr_vector_get(void);
int z_irq_controller_isr_vector_get(void);
#ifdef CONFIG_X2APIC
void z_x2apic_eoi(void);
#endif
static inline void __irq_controller_eoi(void)
static inline void z_irq_controller_eoi(void)
{
#if CONFIG_EOI_FORWARDING_BUG
#if defined(CONFIG_EOI_FORWARDING_BUG)
z_lakemont_eoi();
#else
#elif defined(CONFIG_X2APIC)
z_x2apic_eoi();
#else /* xAPIC */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
#endif
}
#else /* _ASMLANGUAGE */
#if CONFIG_EOI_FORWARDING_BUG
.macro __irq_controller_eoi_macro
call z_lakemont_eoi
.endm
#else
.macro __irq_controller_eoi_macro
#ifdef CONFIG_X2APIC
call z_x2apic_eoi
#else
xorl %eax, %eax /* zeroes eax */
loapic_eoi_reg = (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
movl %eax, loapic_eoi_reg /* tell LOAPIC the IRQ is handled */
#endif
.endm
#endif /* CONFIG_EOI_FORWARDING_BUG */
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_ */

2
soc/x86/intel_quark/quark_se/eoi.c
View file

@ -15,7 +15,7 @@
*/
#include <kernel.h>
#include <arch/x86/irq_controller.h>
#include <drivers/interrupt_controller/sysapic.h>
#include <sys/sys_io.h>
#include <interrupt_controller/ioapic_priv.h>