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dts: bindings: riscv: Add rv32emc variant

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To the 'riscv,isa' property enum.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2023-02-07 13:20:59 +01:00 committed by Carles Cufí
parent dd195d6ea5
commit 034a274d93
1 changed files with 1 additions and 0 deletions
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dts/bindings/riscv/riscv,cpus.yaml
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@ -18,6 +18,7 @@ properties:
required: true required: true
type: string type: string
enum: enum:
- rv32emc
- rv32imac - rv32imac
- rv32imafc - rv32imafc
- rv32imafcb - rv32imafcb