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dts/riscv/openisa: add compatible strings for the RI5CY cores

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This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`

Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-01-18 10:38:08 +01:00 committed by Carles Cufí
parent 6297f3640f
commit 0458ac064c
3 changed files with 20 additions and 2 deletions
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9
dts/bindings/cpu/openisa,ri5cy.yaml Normal file
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@ -0,0 +1,9 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
description: OpenISA RI5CY core
compatible: "openisa,ri5cy"
include: riscv,cpus.yaml

9
dts/bindings/cpu/openisa,zero-ri5cy.yaml Normal file
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@ -0,0 +1,9 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
description: OpenISA Zero-RI5CY core
compatible: "openisa,zero-ri5cy"
include: riscv,cpus.yaml

4
dts/riscv/openisa/rv32m1.dtsi
View file

@ -22,14 +22,14 @@
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "riscv";
compatible = "openisa,ri5cy", "riscv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "riscv";
compatible = "openisa,zero-ri5cy", "riscv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <1>;
};