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arch: arm: cortex_r: Support nested exception detection

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Cortex-A/R does not have hardware supported nested interrupts, but it is
easily emulatable using the nesting level stored in the kernel
structure.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2021-05-18 15:58:01 -04:00 committed by Christopher Friedt
parent 1e153b5091
commit 046f93627c
2 changed files with 6 additions and 0 deletions
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1
arch/arm/core/aarch32/Kconfig
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@ -29,6 +29,7 @@ config CPU_CORTEX_R
bool bool
select CPU_CORTEX select CPU_CORTEX
select HAS_CMSIS_CORE select HAS_CMSIS_CORE
select ARCH_HAS_NESTED_EXCEPTION_DETECTION
select HAS_FLASH_LOAD_OFFSET select HAS_FLASH_LOAD_OFFSET
select ARCH_HAS_USERSPACE if ARM_MPU select ARCH_HAS_USERSPACE if ARM_MPU
select ARCH_HAS_EXTRA_EXCEPTION_INFO select ARCH_HAS_EXTRA_EXCEPTION_INFO

5
arch/arm/include/aarch32/cortex_a_r/exc.h
View file

@ -38,6 +38,11 @@ static ALWAYS_INLINE bool arch_is_in_isr(void)
return (_kernel.cpus[0].nested != 0U); return (_kernel.cpus[0].nested != 0U);
} }
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
return (_kernel.cpus[0].nested > 1U) ? (true) : (false);
}
#if defined(CONFIG_USERSPACE) #if defined(CONFIG_USERSPACE)
/* /*
* This function is used by privileged code to determine if the thread * This function is used by privileged code to determine if the thread