driver: adc: an adc driver for rt1170

reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay

Signed-off-by: Crist Xu <crist.xu@nxp.com>

boards/arm/mimxrt1170_evk/doc/index.rst

@@ -102,6 +102,8 @@ features:
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc                                 |
++-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial port-polling;                |
 |           |            | serial port-interrupt               |
 +-----------+------------+-------------------------------------+

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts

@@ -54,3 +54,7 @@
 		jedec-id = [9d 70 17];
 	};
 };
+
+&lpadc0 {
+	status = "okay";
+};

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml

@@ -19,3 +19,4 @@ supported:
   - counter
   - can
   - spi
+  - adc

drivers/adc/adc_mcux_lpadc.c

@@ -13,7 +13,10 @@
 #include <errno.h>
 #include <drivers/adc.h>
 #include <fsl_lpadc.h>
+
+#if !defined(CONFIG_SOC_SERIES_IMX_RT11XX)
 #include <fsl_power.h>
+#endif
 
 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
 #include <logging/log.h>
@@ -31,6 +34,8 @@ struct mcux_lpadc_config {
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS)\
 	&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
 	lpadc_conversion_average_mode_t calibration_average;
+#else
+	uint32_t calibration_average;
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
 	lpadc_power_level_mode_t power_level;
 	uint32_t offset_a;
@@ -267,11 +272,13 @@ static int mcux_lpadc_init(const struct device *dev)
 	ADC_Type *base = config->base;
 	lpadc_config_t adc_config;
 
+#if !defined(CONFIG_SOC_SERIES_IMX_RT11XX)
 	CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, config->clock_div, true);
 	CLOCK_AttachClk(config->clock_source);
 
 	/* Power up the ADC */
 	POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
+#endif
 
 	LPADC_GetDefaultConfig(&adc_config);
 
@@ -350,12 +357,24 @@ static const struct adc_driver_api mcux_lpadc_driver_api = {
 #define ASSERT_WITHIN_RANGE(val, min, max, str)	\
 	BUILD_ASSERT(val >= min && val <= max, str)
 
+#if defined(CONFIG_SOC_SERIES_IMX_RT11XX)
+#define TO_LPADC_CLOCK_SOURCE(val) 0
+#else
 #define TO_LPADC_CLOCK_SOURCE(val) \
 	MUX_A(CM_ADCASYNCCLKSEL, val)
+#endif
+
 #define TO_LPADC_REFERENCE_VOLTAGE(val) \
 	_DO_CONCAT(kLPADC_ReferenceVoltageAlt, val)
+
+#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS)\
+	&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
 #define TO_LPADC_CALIBRATION_AVERAGE(val) \
 	_DO_CONCAT(kLPADC_ConversionAverage, val)
+#else
+#define TO_LPADC_CALIBRATION_AVERAGE(val) 0
+#endif
+
 #define TO_LPADC_POWER_LEVEL(val) \
 	_DO_CONCAT(kLPADC_PowerLevelAlt, val)
 

dts/arm/nxp/nxp_rt117x.dtsi

@@ -784,6 +784,39 @@
 			compatible = "mmio-sram";
 			reg = <0x202c0000 DT_SIZE_K(512)>;
 		};
+
+		lpadc0: lpadc@40050000 {
+			compatible = "nxp,lpc-lpadc";
+			reg = <0x40050000 0x304>;
+			interrupts = <88 0>;
+			status = "disabled";
+			clk-divider = <8>;
+			clk-source = <0>;
+			voltage-ref= <2>;
+			calibration-average = <128>;
+			power-level = <1>;
+			label = "LPADC_0";
+			offset-value-a = <10>;
+			offset-value-b = <10>;
+			#io-channel-cells = <1>;
+		};
+
+		lpadc1: lpadc@40054000 {
+			compatible = "nxp,lpc-lpadc";
+			reg = <0x40054000 0x304>;
+			interrupts = <89 0>;
+			status = "disabled";
+			clk-divider = <8>;
+			clk-source = <0>;
+			voltage-ref= <2>;
+			calibration-average = <128>;
+			power-level = <1>;
+			label = "LPADC_1";
+			offset-value-a = <10>;
+			offset-value-b = <10>;
+			#io-channel-cells = <1>;
+		};
+
 	};
 };
 

samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay

@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Linaro Limited
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&lpadc0 0>;
+	};
+};

soc/arm/nxp_imx/rt/Kconfig.defconfig.series

@@ -63,6 +63,10 @@ config SPI_MCUX_LPSPI
 	default y if HAS_MCUX_LPSPI
 	depends on SPI
 
+config ADC_MCUX_LPADC
+	default y if HAS_MCUX_LPADC
+	depends on ADC
+
 config WDT_MCUX_IMX_WDOG
 	default y
 	depends on WATCHDOG

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -262,6 +262,7 @@ config SOC_MIMXRT1176_CM7
 	select HAS_MCUX_IGPIO
 	select HAS_MCUX_LPI2C
 	select HAS_MCUX_LPSPI
+	select HAS_MCUX_LPADC
 	select HAS_MCUX_LPUART
 	select HAS_MCUX_GPT
 	select HAS_MCUX_FLEXCAN

tests/drivers/adc/adc_api/src/test_adc.c

@@ -254,7 +254,8 @@
 #define ADC_2ND_CHANNEL_ID	5
 
 #elif defined(CONFIG_BOARD_LPCXPRESSO55S69_CPU0) || \
-	defined(CONFIG_BOARD_LPCXPRESSO55S28)
+	defined(CONFIG_BOARD_LPCXPRESSO55S28) || \
+	defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7)
 #define ADC_DEVICE_NAME		DT_LABEL(DT_INST(0, nxp_lpc_lpadc))
 #define ADC_RESOLUTION		12
 #define ADC_GAIN		ADC_GAIN_1

west.yml

@@ -68,7 +68,7 @@ manifest:
       revision: b4d31f33238713a568e23618845702fadd67386f
       path: modules/hal/nuvoton
     - name: hal_nxp
-      revision: 9a52c50338dcec8ab938f91f62e829898e298d14
+      revision: 4b493d4346e841e786a8daa2eb2ee03cbe5cfd37
       path: modules/hal/nxp
     - name: hal_openisa
       revision: 40d049f69c50b58ea20473bee14cf93f518bf262