drivers: interrupt-controller: Add VIM Interrupt Controller support
Add TI VIM (Vectored Interrupt Manager) interrupt controller support. VIM is a TI specific custom interrupt controller for ARM cores. In J721E soc, VIM aggregates interrupts to Cortex R5 cores. TRM for J721e https://www.ti.com/lit/zip/spruil1 File: spruil1c.pdf VIM: section 6.3.3.6 Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
This commit is contained in:
Prashanth S
Carles Cufí
parent
f0fd9f1713
commit
05fe627d79
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@ -30,6 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32 intc_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3 intc_esp32c3.c)
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zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_VIM intc_vim.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c)
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@ -100,4 +100,6 @@ source "drivers/interrupt_controller/Kconfig.xmc4xxx"
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source "drivers/interrupt_controller/Kconfig.nxp_pint"
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source "drivers/interrupt_controller/Kconfig.vim"
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endmenu
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16
drivers/interrupt_controller/Kconfig.vim
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16
drivers/interrupt_controller/Kconfig.vim
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@ -0,0 +1,16 @@
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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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if CPU_CORTEX_R5
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config VIM
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bool "TI Vectored Interrupt Manager"
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default y
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depends on DT_HAS_TI_VIM_ENABLED
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help
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The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
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and aggregating the interrupt sources for ARM Cortex-R5 processor cores.
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endif # CPU_CORTEX_R5
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151
drivers/interrupt_controller/intc_vim.c
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151
drivers/interrupt_controller/intc_vim.c
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@ -0,0 +1,151 @@
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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_vim
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#include <stdint.h>
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#include <zephyr/arch/arm/aarch32/irq.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/interrupt_controller/intc_vim.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util_macro.h>
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LOG_MODULE_REGISTER(vim);
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unsigned int z_vim_irq_get_active(void)
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{
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uint32_t irq_group_num, irq_bit_num;
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uint32_t actirq, vec_addr;
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/* Reading IRQVEC register, ACTIRQ gets loaded with valid IRQ values */
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vec_addr = sys_read32(VIM_IRQVEC);
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/* ACTIRQ register should be read only after reading IRQVEC register */
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actirq = sys_read32(VIM_ACTIRQ);
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/* Check if the irq number is valid, else return invalid irq number.
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* which will be considered as spurious interrupt
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*/
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if ((actirq & (VIM_ACTIRQ_VALID_MASK)) == 0) {
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return CONFIG_NUM_IRQS + 1;
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}
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(actirq & VIM_PRIIRQ_NUM_MASK);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(actirq & VIM_PRIIRQ_NUM_MASK);
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/* Ack the interrupt in IRQSTS register */
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sys_write32(BIT(irq_bit_num), VIM_IRQSTS(irq_group_num));
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if (irq_group_num > VIM_MAX_GROUP_NUM) {
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return (CONFIG_NUM_IRQS + 1);
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}
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return (actirq & VIM_ACTIRQ_NUM_MASK);
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}
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void z_vim_irq_eoi(unsigned int irq)
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{
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sys_write32(0, VIM_IRQVEC);
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}
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void z_vim_irq_init(void)
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{
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uint32_t num_of_irqs = sys_read32(VIM_INFO_INTERRUPTS_MASK);
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LOG_DBG("VIM: Number of IRQs = %u\n", num_of_irqs);
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}
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void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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uint32_t irq_group_num, irq_bit_num, regval;
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if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX ||
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(flags != IRQ_TYPE_EDGE && flags != IRQ_TYPE_LEVEL)) {
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LOG_ERR("%s: Invalid argument irq = %u prio = %u flags = %u\n",
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__func__, irq, prio, flags);
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return;
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}
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sys_write8(prio, VIM_PRI_INT(irq));
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq);
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regval = sys_read32(VIM_INTTYPE(irq_group_num));
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if (flags == IRQ_TYPE_EDGE) {
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regval |= (BIT(irq_bit_num));
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} else {
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regval &= ~(BIT(irq_bit_num));
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}
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sys_write32(regval, VIM_INTTYPE(irq_group_num));
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}
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void z_vim_irq_enable(unsigned int irq)
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{
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uint32_t irq_group_num, irq_bit_num;
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if (irq > CONFIG_NUM_IRQS) {
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LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq);
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return;
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}
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq);
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sys_write32(BIT(irq_bit_num), VIM_INTR_EN_SET(irq_group_num));
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}
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void z_vim_irq_disable(unsigned int irq)
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{
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uint32_t irq_group_num, irq_bit_num;
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if (irq > CONFIG_NUM_IRQS) {
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LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq);
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return;
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}
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq);
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sys_write32(BIT(irq_bit_num), VIM_INTR_EN_CLR(irq_group_num));
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}
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int z_vim_irq_is_enabled(unsigned int irq)
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{
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uint32_t irq_group_num, irq_bit_num, regval;
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if (irq > CONFIG_NUM_IRQS) {
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LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq);
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return -EINVAL;
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}
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq);
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regval = sys_read32(VIM_INTR_EN_SET(irq_group_num));
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return !!(regval & (BIT(irq_bit_num)));
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}
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void z_vim_arm_enter_irq(int irq)
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{
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uint32_t irq_group_num, irq_bit_num;
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if (irq > CONFIG_NUM_IRQS) {
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LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq);
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return;
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}
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irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq);
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irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq);
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sys_write32(BIT(irq_bit_num), VIM_RAW(irq_group_num));
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}
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22
dts/bindings/interrupt-controller/ti,vim.yaml
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22
dts/bindings/interrupt-controller/ti,vim.yaml
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@ -0,0 +1,22 @@
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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI Vectored Interrupt Manager is a external interrupt controller
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(TI specific IP) which is compatible with R5F VIC port.
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compatible: "ti,vim"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupt-cells:
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- type
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- irq
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- flags
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- priority
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344
include/zephyr/drivers/interrupt_controller/intc_vim.h
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344
include/zephyr/drivers/interrupt_controller/intc_vim.h
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@ -0,0 +1,344 @@
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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_INTC_VIM_H_
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#define ZEPHYR_DRIVERS_INTC_VIM_H_
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#include <stdint.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
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#include <zephyr/sys/util_macro.h>
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#define VIM_BASE_ADDR DT_REG_ADDR(DT_INST(0, ti_vim))
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#define VIM_MAX_IRQ_PER_GROUP (32)
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#define VIM_MAX_GROUP_NUM ((uint32_t)(CONFIG_NUM_IRQS / VIM_MAX_IRQ_PER_GROUP))
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#define VIM_GET_IRQ_GROUP_NUM(n) ((uint32_t)((n) / VIM_MAX_IRQ_PER_GROUP))
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#define VIM_GET_IRQ_BIT_NUM(n) ((uint32_t)((n) % VIM_MAX_IRQ_PER_GROUP))
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#define VIM_PRI_INT_MAX (15)
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#define VIM_PID (VIM_BASE_ADDR + 0x0000)
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#define VIM_INFO (VIM_BASE_ADDR + 0x0004)
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#define VIM_PRIIRQ (VIM_BASE_ADDR + 0x0008)
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#define VIM_PRIFIQ (VIM_BASE_ADDR + 0x000C)
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#define VIM_IRQGSTS (VIM_BASE_ADDR + 0x0010)
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#define VIM_FIQGSTS (VIM_BASE_ADDR + 0x0014)
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#define VIM_IRQVEC (VIM_BASE_ADDR + 0x0018)
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#define VIM_FIQVEC (VIM_BASE_ADDR + 0x001C)
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#define VIM_ACTIRQ (VIM_BASE_ADDR + 0x0020)
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#define VIM_ACTFIQ (VIM_BASE_ADDR + 0x0024)
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#define VIM_DEDVEC (VIM_BASE_ADDR + 0x0030)
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#define VIM_RAW(n) (VIM_BASE_ADDR + (0x400) + ((n) * 0x20))
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#define VIM_STS(n) (VIM_BASE_ADDR + (0x404) + ((n) * 0x20))
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#define VIM_INTR_EN_SET(n) (VIM_BASE_ADDR + (0x408) + ((n) * 0x20))
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#define VIM_INTR_EN_CLR(n) (VIM_BASE_ADDR + (0x40c) + ((n) * 0x20))
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#define VIM_IRQSTS(n) (VIM_BASE_ADDR + (0x410) + ((n) * 0x20))
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#define VIM_FIQSTS(n) (VIM_BASE_ADDR + (0x414) + ((n) * 0x20))
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#define VIM_INTMAP(n) (VIM_BASE_ADDR + (0x418) + ((n) * 0x20))
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#define VIM_INTTYPE(n) (VIM_BASE_ADDR + (0x41c) + ((n) * 0x20))
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#define VIM_PRI_INT(n) (VIM_BASE_ADDR + (0x1000) + ((n) * 0x4))
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#define VIM_VEC_INT(n) (VIM_BASE_ADDR + (0x2000) + ((n) * 0x4))
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/* RAW */
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#define VIM_GRP_RAW_STS_MASK (BIT_MASK(32))
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#define VIM_GRP_RAW_STS_SHIFT (0x00000000U)
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#define VIM_GRP_RAW_STS_RESETVAL (0x00000000U)
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#define VIM_GRP_RAW_STS_MAX (BIT_MASK(32))
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#define VIM_GRP_RAW_RESETVAL (0x00000000U)
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/* STS */
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#define VIM_GRP_STS_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_STS_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_STS_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_STS_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_STS_RESETVAL (0x00000000U)
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/* INTR_EN_SET */
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#define VIM_GRP_INTR_EN_SET_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_INTR_EN_SET_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_INTR_EN_SET_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_INTR_EN_SET_RESETVAL (0x00000000U)
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/* INTR_EN_CLR */
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#define VIM_GRP_INTR_EN_CLR_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_INTR_EN_CLR_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_INTR_EN_CLR_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_INTR_EN_CLR_RESETVAL (0x00000000U)
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/* IRQSTS */
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#define VIM_GRP_IRQSTS_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_IRQSTS_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_IRQSTS_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_IRQSTS_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_IRQSTS_RESETVAL (0x00000000U)
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/* FIQSTS */
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#define VIM_GRP_FIQSTS_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_FIQSTS_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_FIQSTS_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_FIQSTS_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_FIQSTS_RESETVAL (0x00000000U)
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/* INTMAP */
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#define VIM_GRP_INTMAP_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_INTMAP_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_INTMAP_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_INTMAP_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_INTMAP_RESETVAL (0x00000000U)
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/* INTTYPE */
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#define VIM_GRP_INTTYPE_MSK_MASK (BIT_MASK(32))
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#define VIM_GRP_INTTYPE_MSK_SHIFT (0x00000000U)
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#define VIM_GRP_INTTYPE_MSK_RESETVAL (0x00000000U)
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#define VIM_GRP_INTTYPE_MSK_MAX (BIT_MASK(32))
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#define VIM_GRP_INTTYPE_RESETVAL (0x00000000U)
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/* INT */
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#define VIM_PRI_INT_VAL_MASK (BIT_MASK(4))
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#define VIM_PRI_INT_VAL_SHIFT (0x00000000U)
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#define VIM_PRI_INT_VAL_RESETVAL (BIT_MASK(4))
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#define VIM_PRI_INT_VAL_MAX (BIT_MASK(4))
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#define VIM_PRI_INT_RESETVAL (BIT_MASK(4))
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/* INT */
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#define VIM_VEC_INT_VAL_MASK (0xFFFFFFFCU)
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#define VIM_VEC_INT_VAL_SHIFT (0x00000002U)
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#define VIM_VEC_INT_VAL_RESETVAL (0x00000000U)
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#define VIM_VEC_INT_VAL_MAX (BIT_MASK(30))
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#define VIM_VEC_INT_RESETVAL (0x00000000U)
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/* INFO */
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#define VIM_INFO_INTERRUPTS_MASK (BIT_MASK(11))
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#define VIM_INFO_INTERRUPTS_SHIFT (0x00000000U)
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#define VIM_INFO_INTERRUPTS_RESETVAL (0x00000400U)
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#define VIM_INFO_INTERRUPTS_MAX (BIT_MASK(11))
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#define VIM_INFO_RESETVAL (0x00000400U)
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/* PRIIRQ */
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#define VIM_PRIIRQ_VALID_MASK (0x80000000U)
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#define VIM_PRIIRQ_VALID_SHIFT (BIT_MASK(5))
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#define VIM_PRIIRQ_VALID_RESETVAL (0x00000000U)
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#define VIM_PRIIRQ_VALID_MAX (0x00000001U)
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#define VIM_PRIIRQ_VALID_VAL_TRUE (0x1U)
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#define VIM_PRIIRQ_VALID_VAL_FALSE (0x0U)
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#define VIM_PRIIRQ_PRI_MASK (0x000F0000U)
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#define VIM_PRIIRQ_PRI_SHIFT (0x00000010U)
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#define VIM_PRIIRQ_PRI_RESETVAL (0x00000000U)
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#define VIM_PRIIRQ_PRI_MAX (BIT_MASK(4))
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#define VIM_PRIIRQ_NUM_MASK (BIT_MASK(10))
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#define VIM_PRIIRQ_NUM_SHIFT (0x00000000U)
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#define VIM_PRIIRQ_NUM_RESETVAL (0x00000000U)
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#define VIM_PRIIRQ_NUM_MAX (BIT_MASK(10))
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#define VIM_PRIIRQ_RESETVAL (0x00000000U)
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/* PRIFIQ */
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#define VIM_PRIFIQ_VALID_MASK (0x80000000U)
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#define VIM_PRIFIQ_VALID_SHIFT (BIT_MASK(5))
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#define VIM_PRIFIQ_VALID_RESETVAL (0x00000000U)
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#define VIM_PRIFIQ_VALID_MAX (0x00000001U)
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#define VIM_PRIFIQ_VALID_VAL_TRUE (0x1U)
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#define VIM_PRIFIQ_VALID_VAL_FALSE (0x0U)
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#define VIM_PRIFIQ_PRI_MASK (0x000F0000U)
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#define VIM_PRIFIQ_PRI_SHIFT (0x00000010U)
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#define VIM_PRIFIQ_PRI_RESETVAL (0x00000000U)
|
||||
#define VIM_PRIFIQ_PRI_MAX (BIT_MASK(4))
|
||||
|
||||
#define VIM_PRIFIQ_NUM_MASK (BIT_MASK(10))
|
||||
#define VIM_PRIFIQ_NUM_SHIFT (0x00000000U)
|
||||
#define VIM_PRIFIQ_NUM_RESETVAL (0x00000000U)
|
||||
#define VIM_PRIFIQ_NUM_MAX (BIT_MASK(10))
|
||||
|
||||
#define VIM_PRIFIQ_RESETVAL (0x00000000U)
|
||||
|
||||
/* IRQGSTS */
|
||||
|
||||
#define VIM_IRQGSTS_STS_MASK (BIT_MASK(32))
|
||||
#define VIM_IRQGSTS_STS_SHIFT (0x00000000U)
|
||||
#define VIM_IRQGSTS_STS_RESETVAL (0x00000000U)
|
||||
#define VIM_IRQGSTS_STS_MAX (BIT_MASK(32))
|
||||
|
||||
#define VIM_IRQGSTS_RESETVAL (0x00000000U)
|
||||
|
||||
/* FIQGSTS */
|
||||
|
||||
#define VIM_FIQGSTS_STS_MASK (BIT_MASK(32))
|
||||
#define VIM_FIQGSTS_STS_SHIFT (0x00000000U)
|
||||
#define VIM_FIQGSTS_STS_RESETVAL (0x00000000U)
|
||||
#define VIM_FIQGSTS_STS_MAX (BIT_MASK(32))
|
||||
|
||||
#define VIM_FIQGSTS_RESETVAL (0x00000000U)
|
||||
|
||||
/* IRQVEC */
|
||||
|
||||
#define VIM_IRQVEC_ADDR_MASK (0xFFFFFFFCU)
|
||||
#define VIM_IRQVEC_ADDR_SHIFT (0x00000002U)
|
||||
#define VIM_IRQVEC_ADDR_RESETVAL (0x00000000U)
|
||||
#define VIM_IRQVEC_ADDR_MAX (BIT_MASK(30))
|
||||
|
||||
#define VIM_IRQVEC_RESETVAL (0x00000000U)
|
||||
|
||||
/* FIQVEC */
|
||||
|
||||
#define VIM_FIQVEC_ADDR_MASK (0xFFFFFFFCU)
|
||||
#define VIM_FIQVEC_ADDR_SHIFT (0x00000002U)
|
||||
#define VIM_FIQVEC_ADDR_RESETVAL (0x00000000U)
|
||||
#define VIM_FIQVEC_ADDR_MAX (BIT_MASK(30))
|
||||
|
||||
#define VIM_FIQVEC_RESETVAL (0x00000000U)
|
||||
|
||||
/* ACTIRQ */
|
||||
|
||||
#define VIM_ACTIRQ_VALID_MASK (0x80000000U)
|
||||
#define VIM_ACTIRQ_VALID_SHIFT (BIT_MASK(5))
|
||||
#define VIM_ACTIRQ_VALID_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTIRQ_VALID_MAX (0x00000001U)
|
||||
|
||||
#define VIM_ACTIRQ_VALID_VAL_TRUE (0x1U)
|
||||
#define VIM_ACTIRQ_VALID_VAL_FALSE (0x0U)
|
||||
|
||||
#define VIM_ACTIRQ_PRI_MASK (0x000F0000U)
|
||||
#define VIM_ACTIRQ_PRI_SHIFT (0x00000010U)
|
||||
#define VIM_ACTIRQ_PRI_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTIRQ_PRI_MAX (BIT_MASK(4))
|
||||
|
||||
#define VIM_ACTIRQ_NUM_MASK (BIT_MASK(10))
|
||||
#define VIM_ACTIRQ_NUM_SHIFT (0x00000000U)
|
||||
#define VIM_ACTIRQ_NUM_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTIRQ_NUM_MAX (BIT_MASK(10))
|
||||
|
||||
#define VIM_ACTIRQ_RESETVAL (0x00000000U)
|
||||
|
||||
/* ACTFIQ */
|
||||
|
||||
#define VIM_ACTFIQ_VALID_MASK (0x80000000U)
|
||||
#define VIM_ACTFIQ_VALID_SHIFT (BIT_MASK(5))
|
||||
#define VIM_ACTFIQ_VALID_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTFIQ_VALID_MAX (0x00000001U)
|
||||
|
||||
#define VIM_ACTFIQ_VALID_VAL_TRUE (0x1U)
|
||||
#define VIM_ACTFIQ_VALID_VAL_FALSE (0x0U)
|
||||
|
||||
#define VIM_ACTFIQ_PRI_MASK (0x000F0000U)
|
||||
#define VIM_ACTFIQ_PRI_SHIFT (0x00000010U)
|
||||
#define VIM_ACTFIQ_PRI_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTFIQ_PRI_MAX (BIT_MASK(4))
|
||||
|
||||
#define VIM_ACTFIQ_NUM_MASK (BIT_MASK(10))
|
||||
#define VIM_ACTFIQ_NUM_SHIFT (0x00000000U)
|
||||
#define VIM_ACTFIQ_NUM_RESETVAL (0x00000000U)
|
||||
#define VIM_ACTFIQ_NUM_MAX (BIT_MASK(10))
|
||||
|
||||
#define VIM_ACTFIQ_RESETVAL (0x00000000U)
|
||||
|
||||
/* DEDVEC */
|
||||
|
||||
#define VIM_DEDVEC_ADDR_MASK (0xFFFFFFFCU)
|
||||
#define VIM_DEDVEC_ADDR_SHIFT (0x00000002U)
|
||||
#define VIM_DEDVEC_ADDR_RESETVAL (0x00000000U)
|
||||
#define VIM_DEDVEC_ADDR_MAX (BIT_MASK(30))
|
||||
|
||||
#define VIM_DEDVEC_RESETVAL (0x00000000U)
|
||||
|
||||
/*
|
||||
* VIM Driver Interface Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get active interrupt ID.
|
||||
*
|
||||
* @return Returns the ID of an active interrupt.
|
||||
*/
|
||||
unsigned int z_vim_irq_get_active(void);
|
||||
|
||||
/**
|
||||
* @brief Signal end-of-interrupt.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
*/
|
||||
void z_vim_irq_eoi(unsigned int irq);
|
||||
|
||||
/**
|
||||
* @brief Interrupt controller initialization.
|
||||
*/
|
||||
void z_vim_irq_init(void);
|
||||
|
||||
/**
|
||||
* @brief Configure priority, irq type for the interrupt ID.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
* @param prio interrupt priority.
|
||||
* @param flags interrupt flags.
|
||||
*/
|
||||
void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags);
|
||||
|
||||
/**
|
||||
* @brief Enable Interrupt.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
*/
|
||||
void z_vim_irq_enable(unsigned int irq);
|
||||
|
||||
/**
|
||||
* @brief Disable Interrupt.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
*/
|
||||
void z_vim_irq_disable(unsigned int irq);
|
||||
|
||||
/**
|
||||
* @brief Check if an interrupt is enabled.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
*
|
||||
* @retval 0 If interrupt is disabled.
|
||||
* @retval 1 If interrupt is enabled.
|
||||
*/
|
||||
int z_vim_irq_is_enabled(unsigned int irq);
|
||||
|
||||
/**
|
||||
* @brief Raise a software interrupt.
|
||||
*
|
||||
* @param irq interrupt ID.
|
||||
*/
|
||||
void z_vim_arm_enter_irq(int irq);
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_INTC_VIM_H_ */
|
||||
17
include/zephyr/dt-bindings/interrupt-controller/ti-vim.h
Normal file
17
include/zephyr/dt-bindings/interrupt-controller/ti-vim.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* Copyright (C) 2023 BeagleBoard.org Foundation
|
||||
* Copyright (C) 2023 S Prashanth
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDING_TI_VIM_H
|
||||
#define __DT_BINDING_TI_VIM_H
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
#define IRQ_TYPE_LEVEL BIT(1)
|
||||
#define IRQ_TYPE_EDGE BIT(2)
|
||||
|
||||
#define IRQ_DEFAULT_PRIORITY 0xf
|
||||
|
||||
#endif /* __DT_BINDING_TI_VIM_H */
|
||||
|
|
@ -197,6 +197,15 @@ static inline void trigger_irq(int irq)
|
|||
z_mips_enter_irq(irq);
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM)
|
||||
|
||||
extern void z_vim_arm_enter_irq(int);
|
||||
|
||||
static inline void trigger_irq(int irq)
|
||||
{
|
||||
z_vim_arm_enter_irq(irq);
|
||||
}
|
||||
|
||||
#else
|
||||
/* So far, Nios II does not support this */
|
||||
#define NO_TRIGGER_FROM_SW
|
||||
|
|
|
|||
Loading…
Reference in a new issue