drivers: clock_control: imx_ccm_rev2: clean up header file
Peripheral mask is 0xFF00, so reorder the peripheral definitions to be consecutive. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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@ -84,25 +84,25 @@
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#define IMX_CCM_GPT6_CLK 0x1005UL
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/* SAI */
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#define IMX_CCM_SAI1_CLK 0x2000UL
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#define IMX_CCM_SAI2_CLK 0x2001UL
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#define IMX_CCM_SAI3_CLK 0x2002UL
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#define IMX_CCM_SAI4_CLK 0x2003UL
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#define IMX_CCM_SAI1_CLK 0x1100UL
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#define IMX_CCM_SAI2_CLK 0x1101UL
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#define IMX_CCM_SAI3_CLK 0x1102UL
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#define IMX_CCM_SAI4_CLK 0x1103UL
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/* ENET */
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#define IMX_CCM_ENET_CLK 0x3000UL
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#define IMX_CCM_ENET_PLL 0x3001UL
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#define IMX_CCM_ENET_CLK 0x1200UL
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#define IMX_CCM_ENET_PLL 0x1201UL
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/* FLEXSPI */
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#define IMX_CCM_FLEXSPI_CLK 0x4000UL
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#define IMX_CCM_FLEXSPI2_CLK 0x4001UL
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#define IMX_CCM_FLEXSPI_CLK 0x1300UL
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#define IMX_CCM_FLEXSPI2_CLK 0x1301UL
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/* PIT */
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#define IMX_CCM_PIT_CLK 0x5000UL
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#define IMX_CCM_PIT1_CLK 0x5001UL
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#define IMX_CCM_PIT_CLK 0x1400UL
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#define IMX_CCM_PIT1_CLK 0x1401UL
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/* ADC */
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#define IMX_CCM_LPADC1_CLK 0x6000UL
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#define IMX_CCM_LPADC2_CLK 0x6001UL
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#define IMX_CCM_LPADC1_CLK 0x1500UL
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#define IMX_CCM_LPADC2_CLK 0x1501UL
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */
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