xtensa: set toolchain variant per SoC

The toolchain variant per SoC is not always the soc name, so set this
per SoC and use this in the SDK instead of hardcoding the soc name.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2020-10-30 08:55:40 -04:00
parent cc9b64080a
commit 08253db46b
9 changed files with 29 additions and 22 deletions

View file

@ -508,6 +508,7 @@ include(${ZEPHYR_BASE}/cmake/kconfig.cmake)
set(SOC_NAME ${CONFIG_SOC}) set(SOC_NAME ${CONFIG_SOC})
set(SOC_SERIES ${CONFIG_SOC_SERIES}) set(SOC_SERIES ${CONFIG_SOC_SERIES})
set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME})
set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) set(SOC_FAMILY ${CONFIG_SOC_FAMILY})
if("${SOC_SERIES}" STREQUAL "") if("${SOC_SERIES}" STREQUAL "")

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@ -10,28 +10,9 @@ elseif(("${ARCH}" STREQUAL "sparc") AND (${SDK_VERSION} VERSION_LESS 0.12))
else() else()
include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/target.cmake) include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/target.cmake)
# Workaround, FIXME # Workaround, FIXME: Waiting for new SDK.
if("${ARCH}" STREQUAL "xtensa") if("${ARCH}" STREQUAL "xtensa")
if("${SOC_SERIES}" STREQUAL "cavs_v15") set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${SYSROOT_TARGET})
set(SR_XT_TC_SOC intel_apl_adsp) set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
elseif("${SOC_SERIES}" STREQUAL "cavs_v18")
set(SR_XT_TC_SOC intel_s1000)
elseif("${SOC_SERIES}" STREQUAL "cavs_v20")
set(SR_XT_TC_SOC intel_s1000)
elseif("${SOC_SERIES}" STREQUAL "cavs_v25")
set(SR_XT_TC_SOC intel_s1000)
elseif("${SOC_SERIES}" STREQUAL "baytrail_adsp")
set(SR_XT_TC_SOC intel_byt_adsp)
elseif("${SOC_SERIES}" STREQUAL "broadwell_adsp")
set(SR_XT_TC_SOC intel_bdw_adsp)
elseif("${SOC_SERIES}" STREQUAL "intel_s1000")
set(SR_XT_TC_SOC intel_s1000)
elseif("${SOC_NAME}" STREQUAL "sample_controller")
set(SR_XT_TC_SOC sample_controller)
else()
message(FATAL_ERROR "No compiler set for SOC_SERIES ${SOC_SERIES}")
endif()
set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${SYSROOT_TARGET})
set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
endif() endif()
endif() endif()

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@ -3,4 +3,5 @@
# Copyright (c) 2020 Intel Corporation # Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
add_subdirectory(common) add_subdirectory(common)

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@ -7,6 +7,10 @@ config SOC_SERIES
string string
default "cavs_v15" default "cavs_v15"
config SOC_TOOLCHAIN_NAME
string
default "intel_apl_adsp"
config SOC config SOC
string string
default "intel_apl_adsp" if SOC_INTEL_CAVS_APL default "intel_apl_adsp" if SOC_INTEL_CAVS_APL

View file

@ -7,6 +7,10 @@ config SOC_SERIES
string string
default "cavs_v18" default "cavs_v18"
config SOC_TOOLCHAIN_NAME
string
default "intel_s1000"
config SOC config SOC
string string
default "intel_cavs_18" default "intel_cavs_18"

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@ -7,6 +7,10 @@ config SOC_SERIES
string string
default "cavs_v20" default "cavs_v20"
config SOC_TOOLCHAIN_NAME
string
default "intel_s1000"
config SOC config SOC
string string
default "intel_cavs_20" default "intel_cavs_20"

View file

@ -7,6 +7,10 @@ config SOC_SERIES
string string
default "cavs_v25" default "cavs_v25"
config SOC_TOOLCHAIN_NAME
string
default "intel_s1000"
config SOC config SOC
string string
default "intel_cavs_25" default "intel_cavs_25"

View file

@ -12,6 +12,10 @@ config SOC_SERIES
string string
default "intel_s1000" default "intel_s1000"
config SOC_TOOLCHAIN_NAME
string
default "intel_s1000"
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM
default 0 default 0

View file

@ -9,6 +9,10 @@ if SOC_XTENSA_SAMPLE_CONTROLLER
config SOC config SOC
default "sample_controller" default "sample_controller"
config SOC_TOOLCHAIN_NAME
string
default "sample_controller"
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM
default 7 default 7