xtensa: set toolchain variant per SoC
The toolchain variant per SoC is not always the soc name, so set this per SoC and use this in the SDK instead of hardcoding the soc name. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
cc9b64080a
commit
08253db46b
|
@ -508,6 +508,7 @@ include(${ZEPHYR_BASE}/cmake/kconfig.cmake)
|
|||
|
||||
set(SOC_NAME ${CONFIG_SOC})
|
||||
set(SOC_SERIES ${CONFIG_SOC_SERIES})
|
||||
set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME})
|
||||
set(SOC_FAMILY ${CONFIG_SOC_FAMILY})
|
||||
|
||||
if("${SOC_SERIES}" STREQUAL "")
|
||||
|
|
|
@ -10,28 +10,9 @@ elseif(("${ARCH}" STREQUAL "sparc") AND (${SDK_VERSION} VERSION_LESS 0.12))
|
|||
else()
|
||||
include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/target.cmake)
|
||||
|
||||
# Workaround, FIXME
|
||||
# Workaround, FIXME: Waiting for new SDK.
|
||||
if("${ARCH}" STREQUAL "xtensa")
|
||||
if("${SOC_SERIES}" STREQUAL "cavs_v15")
|
||||
set(SR_XT_TC_SOC intel_apl_adsp)
|
||||
elseif("${SOC_SERIES}" STREQUAL "cavs_v18")
|
||||
set(SR_XT_TC_SOC intel_s1000)
|
||||
elseif("${SOC_SERIES}" STREQUAL "cavs_v20")
|
||||
set(SR_XT_TC_SOC intel_s1000)
|
||||
elseif("${SOC_SERIES}" STREQUAL "cavs_v25")
|
||||
set(SR_XT_TC_SOC intel_s1000)
|
||||
elseif("${SOC_SERIES}" STREQUAL "baytrail_adsp")
|
||||
set(SR_XT_TC_SOC intel_byt_adsp)
|
||||
elseif("${SOC_SERIES}" STREQUAL "broadwell_adsp")
|
||||
set(SR_XT_TC_SOC intel_bdw_adsp)
|
||||
elseif("${SOC_SERIES}" STREQUAL "intel_s1000")
|
||||
set(SR_XT_TC_SOC intel_s1000)
|
||||
elseif("${SOC_NAME}" STREQUAL "sample_controller")
|
||||
set(SR_XT_TC_SOC sample_controller)
|
||||
else()
|
||||
message(FATAL_ERROR "No compiler set for SOC_SERIES ${SOC_SERIES}")
|
||||
endif()
|
||||
set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${SYSROOT_TARGET})
|
||||
set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
|
||||
set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${SYSROOT_TARGET})
|
||||
set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
|
||||
endif()
|
||||
endif()
|
||||
|
|
|
@ -3,4 +3,5 @@
|
|||
# Copyright (c) 2020 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
add_subdirectory(common)
|
||||
|
|
|
@ -7,6 +7,10 @@ config SOC_SERIES
|
|||
string
|
||||
default "cavs_v15"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "intel_apl_adsp"
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "intel_apl_adsp" if SOC_INTEL_CAVS_APL
|
||||
|
|
|
@ -7,6 +7,10 @@ config SOC_SERIES
|
|||
string
|
||||
default "cavs_v18"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "intel_s1000"
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "intel_cavs_18"
|
||||
|
|
|
@ -7,6 +7,10 @@ config SOC_SERIES
|
|||
string
|
||||
default "cavs_v20"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "intel_s1000"
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "intel_cavs_20"
|
||||
|
|
|
@ -7,6 +7,10 @@ config SOC_SERIES
|
|||
string
|
||||
default "cavs_v25"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "intel_s1000"
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "intel_cavs_25"
|
||||
|
|
|
@ -12,6 +12,10 @@ config SOC_SERIES
|
|||
string
|
||||
default "intel_s1000"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "intel_s1000"
|
||||
|
||||
config IRQ_OFFLOAD_INTNUM
|
||||
default 0
|
||||
|
||||
|
|
|
@ -9,6 +9,10 @@ if SOC_XTENSA_SAMPLE_CONTROLLER
|
|||
config SOC
|
||||
default "sample_controller"
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "sample_controller"
|
||||
|
||||
config IRQ_OFFLOAD_INTNUM
|
||||
default 7
|
||||
|
||||
|
|
Loading…
Reference in a new issue