drivers: dma: rpi_pico: add support for RaspberryPi Pico DMA
Adding RaspberryPi Pico DMA driver. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This commit is contained in:
TOKITA Hiroshi
Carles Cufí
parent
15535edbfe
commit
08606eac44
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@ -18,3 +18,4 @@ supported:
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- watchdog
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- pwm
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- flash
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- dma
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@ -27,3 +27,4 @@ zephyr_library_sources_ifdef(CONFIG_DMA_GD32 dma_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_ESP32 dma_esp32_gdma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_MCHP_XEC dma_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_XMC4XXX dma_xmc4xxx.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_RPI_PICO dma_rpi_pico.c)
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@ -56,4 +56,6 @@ source "drivers/dma/Kconfig.xec"
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source "drivers/dma/Kconfig.xmc4xxx"
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source "drivers/dma/Kconfig.rpi_pico"
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endif # DMA
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12
drivers/dma/Kconfig.rpi_pico
Normal file
12
drivers/dma/Kconfig.rpi_pico
Normal file
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@ -0,0 +1,12 @@
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# Copyright (c) 2023 Tokita, Hiroshi <tokita.hiroshi@gfujitsu.com>
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# SPDX-License-Identifier: Apache-2.0
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config DMA_RPI_PICO
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bool "Raspberry Pi Pico DMA driver"
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default y
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depends on DT_HAS_RASPBERRYPI_PICO_DMA_ENABLED
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select PICOSDK_USE_DMA
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select PICOSDK_USE_CLAIM
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depends on RESET
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help
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DMA driver for RaspberryPi Pico.
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384
drivers/dma/dma_rpi_pico.c
Normal file
384
drivers/dma/dma_rpi_pico.c
Normal file
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@ -0,0 +1,384 @@
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/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/dt-bindings/dma/rpi_pico_dma.h>
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#include <hardware/dma.h>
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#define DT_DRV_COMPAT raspberrypi_pico_dma
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#define DMA_INT_ERROR_FLAGS \
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(DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS | DMA_CH0_CTRL_TRIG_READ_ERROR_BITS | \
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DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS)
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LOG_MODULE_REGISTER(dma_rpi_pico, CONFIG_DMA_LOG_LEVEL);
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struct dma_rpi_pico_config {
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uint32_t reg;
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uint32_t channels;
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struct reset_dt_spec reset;
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void (*irq_configure)(void);
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uint32_t *irq0_channels;
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size_t irq0_channels_size;
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};
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struct dma_rpi_pico_channel {
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dma_callback_t callback;
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void *user_data;
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uint32_t direction;
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dma_channel_config config;
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void *source_address;
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void *dest_address;
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size_t block_size;
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};
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struct dma_rpi_pico_data {
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struct dma_context ctx;
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struct dma_rpi_pico_channel *channels;
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};
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/*
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* Register access functions
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*/
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static inline void rpi_pico_dma_channel_clear_error_flags(const struct device *dev,
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uint32_t channel)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl &= ~DMA_INT_ERROR_FLAGS;
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}
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static inline uint32_t rpi_pico_dma_channel_get_error_flags(const struct device *dev,
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uint32_t channel)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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return ((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl & DMA_INT_ERROR_FLAGS;
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}
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static inline void rpi_pico_dma_channel_abort(const struct device *dev, uint32_t channel)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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((dma_hw_t *)cfg->reg)->abort = BIT(channel);
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}
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/*
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* Utility functions
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*/
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static inline uint32_t dma_rpi_pico_transfer_size(uint32_t width)
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{
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switch (width) {
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case 4:
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return DMA_SIZE_32;
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case 2:
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return DMA_SIZE_16;
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default:
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return DMA_SIZE_8;
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}
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}
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static inline uint32_t dma_rpi_pico_channel_irq(const struct device *dev, uint32_t channel)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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for (size_t i = 0; i < cfg->irq0_channels_size; i++) {
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if (cfg->irq0_channels[i] == channel) {
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return 0;
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}
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}
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return 1;
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}
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/*
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* API functions
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*/
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static int dma_rpi_pico_config(const struct device *dev, uint32_t channel,
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struct dma_config *dma_cfg)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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struct dma_rpi_pico_data *data = dev->data;
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if (channel >= cfg->channels) {
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LOG_ERR("channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, channel);
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return -EINVAL;
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}
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if (dma_cfg->block_count != 1) {
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LOG_ERR("chained block transfer not supported.");
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return -ENOTSUP;
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}
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if (dma_cfg->channel_priority > 3) {
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LOG_ERR("channel_priority must be < 4 (%" PRIu32 ")", dma_cfg->channel_priority);
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return -EINVAL;
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}
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if (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_DECREMENT) {
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LOG_ERR("source_addr_adj not supported DMA_ADDR_ADJ_DECREMENT");
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return -ENOTSUP;
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}
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if (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT) {
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LOG_ERR("dest_addr_adj not supported DMA_ADDR_ADJ_DECREMENT");
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return -ENOTSUP;
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}
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if (dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_INCREMENT &&
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dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) {
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LOG_ERR("invalid source_addr_adj %" PRIu16, dma_cfg->head_block->source_addr_adj);
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return -ENOTSUP;
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}
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if (dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_INCREMENT &&
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dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) {
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LOG_ERR("invalid dest_addr_adj %" PRIu16, dma_cfg->head_block->dest_addr_adj);
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return -ENOTSUP;
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}
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if (dma_cfg->source_data_size != 1 && dma_cfg->source_data_size != 2 &&
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dma_cfg->source_data_size != 4) {
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LOG_ERR("source_data_size must be 1, 2, or 4 (%" PRIu32 ")",
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dma_cfg->source_data_size);
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return -EINVAL;
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}
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if (dma_cfg->source_data_size != dma_cfg->dest_data_size) {
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return -EINVAL;
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}
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if (dma_cfg->dest_data_size != 1 && dma_cfg->dest_data_size != 2 &&
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dma_cfg->dest_data_size != 4) {
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LOG_ERR("dest_data_size must be 1, 2, or 4 (%" PRIu32 ")", dma_cfg->dest_data_size);
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return -EINVAL;
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}
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if (dma_cfg->channel_direction > PERIPHERAL_TO_MEMORY) {
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LOG_ERR("channel_direction must be MEMORY_TO_MEMORY, "
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"MEMORY_TO_PERIPHERAL or PERIPHERAL_TO_MEMORY (%" PRIu32 ")",
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dma_cfg->channel_direction);
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return -ENOTSUP;
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}
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data->channels[channel].config = dma_channel_get_default_config(channel);
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data->channels[channel].source_address = (void *)dma_cfg->head_block->source_address;
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data->channels[channel].dest_address = (void *)dma_cfg->head_block->dest_address;
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data->channels[channel].block_size = dma_cfg->head_block->block_size;
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channel_config_set_read_increment(&data->channels[channel].config,
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dma_cfg->head_block->source_addr_adj ==
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DMA_ADDR_ADJ_INCREMENT);
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channel_config_set_write_increment(&data->channels[channel].config,
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dma_cfg->head_block->dest_addr_adj ==
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DMA_ADDR_ADJ_INCREMENT);
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channel_config_set_transfer_data_size(
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&data->channels[channel].config,
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dma_rpi_pico_transfer_size(dma_cfg->source_data_size));
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channel_config_set_dreq(&data->channels[channel].config,
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RPI_PICO_DMA_SLOT_TO_DREQ(dma_cfg->dma_slot));
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channel_config_set_high_priority(&data->channels[channel].config,
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!!(dma_cfg->channel_priority));
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data->channels[channel].callback = dma_cfg->dma_callback;
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data->channels[channel].user_data = dma_cfg->user_data;
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data->channels[channel].direction = dma_cfg->channel_direction;
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return 0;
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}
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static int dma_rpi_pico_reload(const struct device *dev, uint32_t ch, uint32_t src, uint32_t dst,
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size_t size)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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struct dma_rpi_pico_data *data = dev->data;
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if (ch >= cfg->channels) {
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LOG_ERR("reload channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, ch);
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return -EINVAL;
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}
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if (dma_channel_is_busy(ch)) {
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return -EBUSY;
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}
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data->channels[ch].source_address = (void *)src;
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data->channels[ch].dest_address = (void *)dst;
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data->channels[ch].block_size = size;
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dma_channel_configure(ch, &data->channels[ch].config, data->channels[ch].dest_address,
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data->channels[ch].source_address, data->channels[ch].block_size,
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true);
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return 0;
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}
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static int dma_rpi_pico_start(const struct device *dev, uint32_t ch)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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struct dma_rpi_pico_data *data = dev->data;
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if (ch >= cfg->channels) {
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LOG_ERR("start channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, ch);
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return -EINVAL;
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}
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dma_irqn_acknowledge_channel(dma_rpi_pico_channel_irq(dev, ch), ch);
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dma_irqn_set_channel_enabled(dma_rpi_pico_channel_irq(dev, ch), ch, true);
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dma_channel_configure(ch, &data->channels[ch].config, data->channels[ch].dest_address,
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data->channels[ch].source_address, data->channels[ch].block_size,
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true);
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return 0;
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}
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static int dma_rpi_pico_stop(const struct device *dev, uint32_t ch)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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if (ch >= cfg->channels) {
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LOG_ERR("stop channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, ch);
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return -EINVAL;
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}
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dma_irqn_set_channel_enabled(dma_rpi_pico_channel_irq(dev, ch), ch, false);
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rpi_pico_dma_channel_clear_error_flags(dev, ch);
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/*
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* Considering the possibility of being called in an interrupt context,
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* it does not wait until the abort bit becomes clear.
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* Ensure the busy status is canceled with dma_get_status
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* before the next transfer starts.
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*/
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rpi_pico_dma_channel_abort(dev, ch);
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return 0;
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}
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static int dma_rpi_pico_get_status(const struct device *dev, uint32_t ch, struct dma_status *stat)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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struct dma_rpi_pico_data *data = dev->data;
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if (ch >= cfg->channels) {
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LOG_ERR("channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, ch);
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return -EINVAL;
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}
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stat->pending_length = 0;
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stat->dir = data->channels[ch].direction;
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stat->busy = dma_channel_is_busy(ch);
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return 0;
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}
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static bool dma_rpi_pico_api_chan_filter(const struct device *dev, int ch, void *filter_param)
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{
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uint32_t filter;
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if (!filter_param) {
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LOG_ERR("filter_param must not be NULL");
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return false;
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}
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filter = *((uint32_t *)filter_param);
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return (filter & BIT(ch));
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}
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static int dma_rpi_pico_init(const struct device *dev)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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(void)reset_line_toggle_dt(&cfg->reset);
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cfg->irq_configure();
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return 0;
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}
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static void dma_rpi_pico_isr(const struct device *dev)
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{
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const struct dma_rpi_pico_config *cfg = dev->config;
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struct dma_rpi_pico_data *data = dev->data;
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int err = 0;
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for (uint32_t i = 0; i < cfg->channels; i++) {
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if (!dma_irqn_get_channel_status(dma_rpi_pico_channel_irq(dev, i), i)) {
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continue;
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}
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if (rpi_pico_dma_channel_get_error_flags(dev, i)) {
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err = -EIO;
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}
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dma_irqn_acknowledge_channel(dma_rpi_pico_channel_irq(dev, i), i);
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dma_irqn_set_channel_enabled(dma_rpi_pico_channel_irq(dev, i), i, false);
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rpi_pico_dma_channel_clear_error_flags(dev, i);
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if (data->channels[i].callback) {
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data->channels[i].callback(dev, data->channels[i].user_data, i, err);
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}
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}
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}
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static const struct dma_driver_api dma_rpi_pico_driver_api = {
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.config = dma_rpi_pico_config,
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.reload = dma_rpi_pico_reload,
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.start = dma_rpi_pico_start,
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.stop = dma_rpi_pico_stop,
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.get_status = dma_rpi_pico_get_status,
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.chan_filter = dma_rpi_pico_api_chan_filter,
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};
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#define IRQ_CONFIGURE(n, inst) \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, n, irq), DT_INST_IRQ_BY_IDX(inst, n, priority), \
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dma_rpi_pico_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(inst, n, irq));
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#define CONFIGURE_ALL_IRQS(inst, n) LISTIFY(n, IRQ_CONFIGURE, (), inst)
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#define RPI_PICO_DMA_INIT(inst) \
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static void dma_rpi_pico##inst##_irq_configure(void) \
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{ \
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CONFIGURE_ALL_IRQS(inst, DT_NUM_IRQS(DT_DRV_INST(inst))); \
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} \
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static uint32_t dma_rpi_pico##inst##_irq0_channels[] = \
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DT_INST_PROP_OR(inst, irq0_channels, {0}); \
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static const struct dma_rpi_pico_config dma_rpi_pico##inst##_config = { \
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.reg = DT_INST_REG_ADDR(inst), \
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.channels = DT_INST_PROP(inst, dma_channels), \
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.reset = RESET_DT_SPEC_INST_GET(inst), \
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.irq_configure = dma_rpi_pico##inst##_irq_configure, \
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.irq0_channels = dma_rpi_pico##inst##_irq0_channels, \
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.irq0_channels_size = ARRAY_SIZE(dma_rpi_pico##inst##_irq0_channels), \
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}; \
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static struct dma_rpi_pico_channel \
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dma_rpi_pico##inst##_channels[DT_INST_PROP(inst, dma_channels)]; \
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ATOMIC_DEFINE(dma_rpi_pico_atomic##inst, DT_INST_PROP(inst, dma_channels)); \
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static struct dma_rpi_pico_data dma_rpi_pico##inst##_data = { \
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.ctx = \
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{ \
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.magic = DMA_MAGIC, \
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.atomic = dma_rpi_pico_atomic##inst, \
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.dma_channels = DT_INST_PROP(inst, dma_channels), \
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}, \
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.channels = dma_rpi_pico##inst##_channels, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &dma_rpi_pico_init, NULL, &dma_rpi_pico##inst##_data, \
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&dma_rpi_pico##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \
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&dma_rpi_pico_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(RPI_PICO_DMA_INIT)
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@ -186,6 +186,19 @@
|
|||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
dma: dma@50000000 {
|
||||
compatible = "raspberrypi,pico-dma";
|
||||
reg = <0x50000000 DT_SIZE_K(64)>;
|
||||
resets = <&reset RPI_PICO_RESETS_RESET_DMA>;
|
||||
clocks = <&system_clk>;
|
||||
interrupts = <11 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
|
||||
<12 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
|
||||
interrupt-names = "dma0", "dma1";
|
||||
dma-channels = <12>;
|
||||
status = "disabled";
|
||||
#dma-cells = <3>;
|
||||
};
|
||||
|
||||
vreg: vreg@40064000 {
|
||||
compatible = "raspberrypi,core-supply-regulator";
|
||||
reg = <0x40064000 1>;
|
||||
|
|
|
|||
42
dts/bindings/dma/raspberrypi,pico-dma.yaml
Normal file
42
dts/bindings/dma/raspberrypi,pico-dma.yaml
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Raspberry Pi Pico GPIO
|
||||
|
||||
channel: Select channel for data transmitting
|
||||
|
||||
slot: Select peripheral data request
|
||||
Use the definitions defined in `zephyr/dt-bindings/dma/rpi_pico_dma.h`.
|
||||
|
||||
channel-config: A 32bit mask specifying the DMA channel configuration
|
||||
- bit 3: Enable Quiet IRQ
|
||||
- bit 1: Enable Byte Swap
|
||||
- bit 0: Enable High Priority
|
||||
|
||||
compatible: "raspberrypi,pico-dma"
|
||||
|
||||
include: [dma-controller.yaml, reset-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
dma-channels:
|
||||
required: true
|
||||
|
||||
irq0-channels:
|
||||
type: uint8-array
|
||||
default: [0, 2, 4, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
|
||||
description: Channels list that uses the irq0
|
||||
|
||||
"#dma-cells":
|
||||
const: 3
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
- slot
|
||||
- channel-config
|
||||
64
include/zephyr/dt-bindings/dma/rpi_pico_dma.h
Normal file
64
include/zephyr/dt-bindings/dma/rpi_pico_dma.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_
|
||||
|
||||
/*
|
||||
* Use lower 6-bit of inverted DREQ value for `slot` cell.
|
||||
* Need to be able to work for memory-to-memory transfer
|
||||
* with zero, which is the default value.
|
||||
*/
|
||||
#define RPI_PICO_DMA_SLOT_TO_DREQ(s) (~(s)&0x3F)
|
||||
#define RPI_PICO_DMA_DREQ_TO_SLOT RPI_PICO_DMA_SLOT_TO_DREQ
|
||||
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x00)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x01)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x02)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x03)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x04)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x05)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x06)
|
||||
#define RPI_PICO_DMA_SLOT_PIO0_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x07)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x08)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x09)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0A)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0B)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x0C)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x0D)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0E)
|
||||
#define RPI_PICO_DMA_SLOT_PIO1_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0F)
|
||||
#define RPI_PICO_DMA_SLOT_SPI0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x10)
|
||||
#define RPI_PICO_DMA_SLOT_SPI0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x11)
|
||||
#define RPI_PICO_DMA_SLOT_SPI1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x12)
|
||||
#define RPI_PICO_DMA_SLOT_SPI1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x13)
|
||||
#define RPI_PICO_DMA_SLOT_UART0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x14)
|
||||
#define RPI_PICO_DMA_SLOT_UART0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x15)
|
||||
#define RPI_PICO_DMA_SLOT_UART1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x16)
|
||||
#define RPI_PICO_DMA_SLOT_UART1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x17)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP0 RPI_PICO_DMA_DREQ_TO_SLOT(0x18)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP1 RPI_PICO_DMA_DREQ_TO_SLOT(0x19)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP2 RPI_PICO_DMA_DREQ_TO_SLOT(0x1A)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP3 RPI_PICO_DMA_DREQ_TO_SLOT(0x1B)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP4 RPI_PICO_DMA_DREQ_TO_SLOT(0x1C)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP5 RPI_PICO_DMA_DREQ_TO_SLOT(0x1D)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP6 RPI_PICO_DMA_DREQ_TO_SLOT(0x1E)
|
||||
#define RPI_PICO_DMA_SLOT_PWM_WRAP7 RPI_PICO_DMA_DREQ_TO_SLOT(0x1F)
|
||||
#define RPI_PICO_DMA_SLOT_I2C0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x30)
|
||||
#define RPI_PICO_DMA_SLOT_I2C0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x31)
|
||||
#define RPI_PICO_DMA_SLOT_I2C1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x32)
|
||||
#define RPI_PICO_DMA_SLOT_I2C1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x33)
|
||||
#define RPI_PICO_DMA_SLOT_ADC RPI_PICO_DMA_DREQ_TO_SLOT(0x34)
|
||||
#define RPI_PICO_DMA_SLOT_XIP_STREAM RPI_PICO_DMA_DREQ_TO_SLOT(0x35)
|
||||
#define RPI_PICO_DMA_SLOT_XIP_SSITX RPI_PICO_DMA_DREQ_TO_SLOT(0x36)
|
||||
#define RPI_PICO_DMA_SLOT_XIP_SSIRX RPI_PICO_DMA_DREQ_TO_SLOT(0x37)
|
||||
#define RPI_PICO_DMA_SLOT_DMA_TIMER0 RPI_PICO_DMA_DREQ_TO_SLOT(0x3B)
|
||||
#define RPI_PICO_DMA_SLOT_DMA_TIMER1 RPI_PICO_DMA_DREQ_TO_SLOT(0x3C)
|
||||
#define RPI_PICO_DMA_SLOT_DMA_TIMER2 RPI_PICO_DMA_DREQ_TO_SLOT(0x3D)
|
||||
#define RPI_PICO_DMA_SLOT_DMA_TIMER3 RPI_PICO_DMA_DREQ_TO_SLOT(0x3E)
|
||||
#define RPI_PICO_DMA_SLOT_FORCE RPI_PICO_DMA_DREQ_TO_SLOT(0x3F)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_ */
|
||||
Loading…
Reference in a new issue