pinmux: sam0: add a pinmux driver for the SAM0 series.

Pin multiplexing is a function of the PORT peripheral.  This change
defines a separate pinmux device at the same address as the PORTs
themselves.

Signed-off-by: Michael Hope <mlhx@google.com>

boards/arm/arduino_zero/dts.fixup

@@ -45,4 +45,10 @@
 #define CONFIG_WDT_SAM0_LABEL ATMEL_SAM0_WATCHDOG_40001000_LABEL
 #define CONFIG_WDT_SAM0_BASE_ADDRESS ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS
 
+#define CONFIG_PINMUX_SAM0_A_BASE_ADDRESS ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS
+#define CONFIG_PINMUX_SAM0_A_LABEL ATMEL_SAM0_PINMUX_41004400_LABEL
+
+#define CONFIG_PINMUX_SAM0_B_BASE_ADDRESS ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS
+#define CONFIG_PINMUX_SAM0_B_LABEL ATMEL_SAM0_PINMUX_41004480_LABEL
+
 #define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

drivers/pinmux/CMakeLists.txt

@@ -7,6 +7,7 @@ zephyr_sources_ifdef(CONFIG_PINMUX_MCUX            pinmux_mcux.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC        pinmux_mcux_lpc.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_QMSI            pinmux_qmsi.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_STM32           stm32/pinmux_stm32.c)
+zephyr_sources_ifdef(CONFIG_PINMUX_SAM0            pinmux_sam0.c)
 
 # "runtime" pinmux
 add_subdirectory_ifdef(CONFIG_PINMUX_DEV dev)

drivers/pinmux/Kconfig

@@ -60,4 +60,6 @@ source "drivers/pinmux/Kconfig.cc2650"
 
 source "drivers/pinmux/Kconfig.esp32"
 
+source "drivers/pinmux/Kconfig.sam0"
+
 endif # PINMUX

drivers/pinmux/Kconfig.sam0

@@ -0,0 +1,11 @@
+# Kconfig.sam0 - Atmel SAM0 pinmux configuration options
+#
+# Copyright (c) 2018 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig PINMUX_SAM0
+	bool "Atmel SAM0 pin multiplexer driver"
+	depends on PINMUX && SOC_FAMILY_SAM0
+	default n
+	help
+	  Enable support for the Atmel SAM0 PORT pin multiplexer.

drivers/pinmux/pinmux_sam0.c

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2018 Google LLC.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <pinmux.h>
+#include <soc.h>
+
+struct pinmux_sam0_config {
+	PortGroup *regs;
+};
+
+static int pinmux_sam0_set(struct device *dev, u32_t pin, u32_t func)
+{
+	const struct pinmux_sam0_config *cfg = dev->config->config_info;
+	bool odd_pin = pin & 1;
+	int idx = pin / 2;
+
+	/* Each pinmux register holds the config for two pins.  The
+	 * even numbered pin goes in the bits 0..3 and the odd
+	 * numbered pin in bits 4..7.
+	 */
+	if (odd_pin) {
+		cfg->regs->PMUX[idx].bit.PMUXO = func;
+	} else {
+		cfg->regs->PMUX[idx].bit.PMUXE = func;
+	}
+	cfg->regs->PINCFG[pin].bit.PMUXEN = 1;
+
+	return 0;
+}
+
+static int pinmux_sam0_get(struct device *dev, u32_t pin, u32_t *func)
+{
+	const struct pinmux_sam0_config *cfg = dev->config->config_info;
+	bool odd_pin = pin & 1;
+	int idx = pin / 2;
+
+	if (odd_pin) {
+		*func = cfg->regs->PMUX[idx].bit.PMUXO;
+	} else {
+		*func = cfg->regs->PMUX[idx].bit.PMUXE;
+	}
+
+	return 0;
+}
+
+static int pinmux_sam0_pullup(struct device *dev, u32_t pin, u8_t func)
+{
+	return -ENOTSUP;
+}
+
+static int pinmux_sam0_input(struct device *dev, u32_t pin, u8_t func)
+{
+	return -ENOTSUP;
+}
+
+static int pinmux_sam0_init(struct device *dev)
+{
+	/* Nothing to do.  The GPIO clock is enabled at reset. */
+	return 0;
+}
+
+const struct pinmux_driver_api pinmux_sam0_api = {
+	.set = pinmux_sam0_set,
+	.get = pinmux_sam0_get,
+	.pullup = pinmux_sam0_pullup,
+	.input = pinmux_sam0_input,
+};
+
+#if CONFIG_PINMUX_SAM0_A_BASE_ADDRESS
+static const struct pinmux_sam0_config pinmux_sam0_config_0 = {
+	.regs = (PortGroup *)CONFIG_PINMUX_SAM0_A_BASE_ADDRESS,
+};
+
+DEVICE_AND_API_INIT(pinmux_sam0_0, CONFIG_PINMUX_SAM0_A_LABEL,
+		    pinmux_sam0_init, NULL, &pinmux_sam0_config_0,
+		    PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY,
+		    &pinmux_sam0_api);
+#endif
+
+#if CONFIG_PINMUX_SAM0_B_BASE_ADDRESS
+static const struct pinmux_sam0_config pinmux_sam0_config_1 = {
+	.regs = (PortGroup *)CONFIG_PINMUX_SAM0_B_BASE_ADDRESS,
+};
+
+DEVICE_AND_API_INIT(pinmux_sam0_1, CONFIG_PINMUX_SAM0_B_LABEL,
+		    pinmux_sam0_init, NULL, &pinmux_sam0_config_1,
+		    PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY,
+		    &pinmux_sam0_api);
+#endif

dts/arm/atmel/samd21.dtsi

@@ -42,6 +42,18 @@
 			};
 		};
 
+		pinmux_a: pinmux@41004400 {
+			compatible = "atmel,sam0-pinmux";
+			reg = <0x41004400 0x80>;
+			label = "PINMUX_A";
+		};
+
+		pinmux_b: pinmux@41004480 {
+			compatible = "atmel,sam0-pinmux";
+			reg = <0x41004480 0x80>;
+			label = "PINMUX_B";
+		};
+
 		wdog: watchdog@40001000 {
 			compatible = "atmel,sam0-watchdog";
 			reg = <0x40001000 9>;

dts/bindings/pinctrl/atmel,sam0-pinmux.yaml

@@ -0,0 +1,34 @@
+---
+title: Atmel SAM0 PINMUX
+id: atmel,sam0-pinmux
+version: 0.1
+
+description: >
+    This binding gives a base representation of the Atmel SAM0 PINMUX
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "atmel,sam0-pinmux"
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+cell_string: PINMUX
+
+"#cells":
+  - pin
+  - function
+
+...