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drivers/pinmux: stm32: Provide unique API to stm32_dt_pinctrl

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Set stm32_dt_pinctrl_configure function as the unique entry point
to STM32 DT pinctrl management.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-10-16 17:20:00 +02:00 committed by Kumar Gala
parent f44e931b0c
commit 0b9c584ec1
9 changed files with 101 additions and 131 deletions
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12
drivers/adc/adc_stm32.c
View file

@ -549,6 +549,7 @@ static int adc_stm32_init(const struct device *dev)
const struct device *clk = const struct device *clk =
device_get_binding(STM32_CLOCK_CONTROL_NAME); device_get_binding(STM32_CLOCK_CONTROL_NAME);
ADC_TypeDef *adc = (ADC_TypeDef *)config->base; ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
int err;
LOG_DBG("Initializing...."); LOG_DBG("Initializing....");
@ -568,10 +569,13 @@ static int adc_stm32_init(const struct device *dev)
return -EIO; return -EIO;
} }
/* configure pinmux */ /* Configure dt provided device signals when available */
if (config->pinctrl_len != 0U) { err = stm32_dt_pinctrl_configure(config->pinctrl,
stm32_dt_pinctrl_configure(config->pinctrl, config->pinctrl_len,
config->pinctrl_len); (uint32_t)config->base);
if (err < 0) {
LOG_ERR("ADC pinctrl setup failed (%d)", err);
return err;
} }
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \

23
drivers/can/can_stm32.c
View file

@ -410,22 +410,13 @@ static int can_stm32_init(const struct device *dev)
return -EIO; return -EIO;
} }
/* configure pinmux */ /* Configure dt provided device signals when available */
if (cfg->pinctrl_len != 0U) { ret = stm32_dt_pinctrl_configure(cfg->pinctrl,
cfg->pinctrl_len,
if (IS_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl))) { (uint32_t)cfg->can);
int remap; if (ret < 0) {
/* Check remap configuration is coherent across pins */ LOG_ERR("CAN pinctrl setup failed (%d)", ret);
remap = stm32_dt_pinctrl_remap_check(cfg->pinctrl, return ret;
cfg->pinctrl_len);
if (remap < 0) {
return remap;
}
stm32_dt_pinctrl_remap_set((uint32_t)cfg->can, remap);
}
stm32_dt_pinctrl_configure(cfg->pinctrl, cfg->pinctrl_len);
} }
ret = can_leave_sleep_mode(can); ret = can_leave_sleep_mode(can);

11
drivers/dac/dac_stm32.c
View file

@ -117,6 +117,7 @@ static int dac_stm32_channel_setup(const struct device *dev,
static int dac_stm32_init(const struct device *dev) static int dac_stm32_init(const struct device *dev)
{ {
const struct dac_stm32_cfg *cfg = dev->config; const struct dac_stm32_cfg *cfg = dev->config;
int err;
/* enable clock for subsystem */ /* enable clock for subsystem */
const struct device *clk = const struct device *clk =
@ -127,9 +128,13 @@ static int dac_stm32_init(const struct device *dev)
return -EIO; return -EIO;
} }
/* configure pinmux */ /* Configure dt provided device signals when available */
if (cfg->pinctrl_len != 0U) { err = stm32_dt_pinctrl_configure(cfg->pinctrl,
stm32_dt_pinctrl_configure(cfg->pinctrl, cfg->pinctrl_len); cfg->pinctrl_len,
(uint32_t)cfg->base);
if (err < 0) {
LOG_ERR("DAC pinctrl setup failed (%d)", err);
return err;
} }
return 0; return 0;

23
drivers/i2c/i2c_ll_stm32.c
View file

@ -188,22 +188,13 @@ static int i2c_stm32_init(const struct device *dev)
cfg->irq_config_func(dev); cfg->irq_config_func(dev);
#endif #endif
if (cfg->pinctrl_list_size != 0) { /* Configure dt provided device signals when available */
ret = stm32_dt_pinctrl_configure(cfg->pinctrl_list,
if (IS_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl))) { cfg->pinctrl_list_size,
int remap; (uint32_t)cfg->i2c);
/* Check remap configuration is coherent across pins */ if (ret < 0) {
remap = stm32_dt_pinctrl_remap_check(cfg->pinctrl_list, LOG_ERR("I2C pinctrl setup failed (%d)", ret);
cfg->pinctrl_list_size); return ret;
if (remap < 0) {
return remap;
}
stm32_dt_pinctrl_remap_set((uint32_t)cfg->i2c, remap);
}
stm32_dt_pinctrl_configure(cfg->pinctrl_list,
cfg->pinctrl_list_size);
} }
/* /*

60
drivers/pinmux/stm32/pinmux_stm32.c
View file

@ -122,15 +122,31 @@ static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
* *
* @param *pinctrl pointer to soc_gpio_pinctrl list * @param *pinctrl pointer to soc_gpio_pinctrl list
* @param list_size list size * @param list_size list size
* @param base device base register value
*
* @return 0 on success, -EINVAL otherwise
*/ */
int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
void stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl, size_t list_size, uint32_t base)
size_t list_size)
{ {
const struct device *clk; const struct device *clk;
uint32_t pin, mux; uint32_t pin, mux;
uint32_t func = 0; uint32_t func = 0;
if (!list_size) {
/* Empty pinctrl. Exit */
return 0;
}
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
if (!stm32_dt_pinctrl_remap(pinctrl, list_size, base)) {
/* Wrong remap config. Exit */
return -EINVAL;
}
#else
ARG_UNUSED(base);
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
/* make sure to enable port clock first */ /* make sure to enable port clock first */
clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
@ -177,23 +193,26 @@ void stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
stm32_pin_configure(pin, func, STM32_DT_PINMUX_FUNC(mux)); stm32_pin_configure(pin, func, STM32_DT_PINMUX_FUNC(mux));
} }
return 0;
} }
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
/** /**
* @brief Helper function to check provided pinctrl remap configuration (Pin * @brief Helper function to check and apply provided pinctrl remap
* remapping configuration should be the same on all pins) * configuration
*
* Check operation verifies that pin remapping configuration is the same on all
* pins. If configuration is valid AFIO clock is enabled and remap is applied
* *
* @param *pinctrl pointer to soc_gpio_pinctrl list * @param *pinctrl pointer to soc_gpio_pinctrl list
* @param list_size list size * @param list_size list size
* @param base device base register value
* *
* @return remap value on success, -EINVAL otherwise * @return 0 on success, -EINVAL otherwise
*/ */
int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
int stm32_dt_pinctrl_remap_check(const struct soc_gpio_pinctrl *pinctrl, size_t list_size, uint32_t base)
size_t list_size)
{ {
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
int remap; int remap;
uint32_t mux; uint32_t mux;
@ -204,22 +223,11 @@ int stm32_dt_pinctrl_remap_check(const struct soc_gpio_pinctrl *pinctrl,
remap = STM32_DT_PINMUX_REMAP(mux); remap = STM32_DT_PINMUX_REMAP(mux);
if (STM32_DT_PINMUX_REMAP(mux) != remap) { if (STM32_DT_PINMUX_REMAP(mux) != remap) {
remap = -EINVAL; return -EINVAL;
break;
} }
} }
return remap; /* A valid remapping configuration is available */
#else
return 0;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
}
void stm32_dt_pinctrl_remap_set(uint32_t base, int remap)
{
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
/* A valid remapping configuration is provided */
/* Apply remapping before proceeding with pin configuration */ /* Apply remapping before proceeding with pin configuration */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO); LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
@ -423,8 +431,10 @@ void stm32_dt_pinctrl_remap_set(uint32_t base, int remap)
#endif #endif
} }
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */ return 0;
} }
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
/** /**
* @brief pin setup * @brief pin setup

34
drivers/pinmux/stm32/pinmux_stm32.h
View file

@ -143,31 +143,31 @@ void stm32_setup_pins(const struct pin_config *pinconf,
* format * format
* *
* @param *pinctrl pointer to soc_gpio_pinctrl list * @param *pinctrl pointer to soc_gpio_pinctrl list
* @param list_size provided list size * @param list_size list size
* @param base device base register value
* *
* @return 0 on success, -EINVAL otherwise
*/ */
void stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl, int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
size_t list_size); size_t list_size, uint32_t base);
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
/** /**
* @brief Helper function to check provided pinctrl remap configuration (Pin * @brief Helper function to check and apply provided pinctrl remap
* remapping configuration should be the same on all pins) * configuration
*
* Check operation verifies that pin remapping configuration is the same on all
* pins. If configuration is valid AFIO clock is enabled and remap is applied
* *
* @param *pinctrl pointer to soc_gpio_pinctrl list * @param *pinctrl pointer to soc_gpio_pinctrl list
* @param list_size provided list size * @param list_size list size
* @param base device base register value
* *
* @return remap value on success, -EINVAL otherwise * @return 0 value on success, -EINVAL otherwise
*/ */
int stm32_dt_pinctrl_remap_check(const struct soc_gpio_pinctrl *pinctrl, int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
size_t list_size); size_t list_size, uint32_t base);
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
/**
* @brief
*
* @param
* @param
*/
void stm32_dt_pinctrl_remap_set(uint32_t base, int remap);
/* common pinmux device name for all STM32 chips */ /* common pinmux device name for all STM32 chips */
#define STM32_PINMUX_NAME "stm32-pinmux" #define STM32_PINMUX_NAME "stm32-pinmux"

23
drivers/pwm/pwm_stm32.c
View file

@ -282,23 +282,12 @@ static int pwm_stm32_init(const struct device *dev)
} }
/* configure pinmux */ /* configure pinmux */
if (cfg->pinctrl_len != 0U) { r = stm32_dt_pinctrl_configure(cfg->pinctrl,
cfg->pinctrl_len,
if (IS_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl))) { (uint32_t)cfg->timer);
int remap; if (r < 0) {
LOG_ERR("PWM pinctrl setup failed (%d)", r);
remap = stm32_dt_pinctrl_remap_check(cfg->pinctrl, return r;
cfg->pinctrl_len);
if (remap < 0) {
LOG_ERR("pinctrl remap check failed (%d)",
remap);
return remap;
}
stm32_dt_pinctrl_remap_set((uint32_t)cfg->timer, remap);
}
stm32_dt_pinctrl_configure(cfg->pinctrl, cfg->pinctrl_len);
} }
/* initialize timer */ /* initialize timer */

23
drivers/serial/uart_stm32.c
View file

@ -670,6 +670,7 @@ static int uart_stm32_init(const struct device *dev)
USART_TypeDef *UartInstance = UART_STRUCT(dev); USART_TypeDef *UartInstance = UART_STRUCT(dev);
uint32_t ll_parity; uint32_t ll_parity;
uint32_t ll_datawidth; uint32_t ll_datawidth;
int err;
__uart_stm32_get_clock(dev); __uart_stm32_get_clock(dev);
/* enable clock */ /* enable clock */
@ -679,23 +680,11 @@ static int uart_stm32_init(const struct device *dev)
} }
/* Configure dt provided device signals when available */ /* Configure dt provided device signals when available */
if (config->pinctrl_list_size != 0) { err = stm32_dt_pinctrl_configure(config->pinctrl_list,
if (IS_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl))) { config->pinctrl_list_size,
int remap; (uint32_t)UART_STRUCT(dev));
/* Check remap configuration is coherent across pins */ if (err < 0) {
remap = stm32_dt_pinctrl_remap_check( return err;
config->pinctrl_list,
config->pinctrl_list_size);
if (remap < 0) {
return remap;
}
stm32_dt_pinctrl_remap_set((uint32_t)UART_STRUCT(dev),
remap);
}
stm32_dt_pinctrl_configure(config->pinctrl_list,
config->pinctrl_list_size);
} }
LL_USART_Disable(UartInstance); LL_USART_Disable(UartInstance);

23
drivers/spi/spi_ll_stm32.c
View file

@ -789,6 +789,7 @@ static int spi_stm32_init(const struct device *dev)
{ {
struct spi_stm32_data *data __attribute__((unused)) = dev->data; struct spi_stm32_data *data __attribute__((unused)) = dev->data;
const struct spi_stm32_config *cfg = dev->config; const struct spi_stm32_config *cfg = dev->config;
int err;
__ASSERT_NO_MSG(device_get_binding(STM32_CLOCK_CONTROL_NAME)); __ASSERT_NO_MSG(device_get_binding(STM32_CLOCK_CONTROL_NAME));
@ -799,22 +800,12 @@ static int spi_stm32_init(const struct device *dev)
} }
/* Configure dt provided device signals when available */ /* Configure dt provided device signals when available */
if (cfg->pinctrl_list_size != 0) { err = stm32_dt_pinctrl_configure(cfg->pinctrl_list,
cfg->pinctrl_list_size,
if (IS_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl))) { (uint32_t)cfg->spi);
int remap; if (err < 0) {
/* Check remap configuration is coherent across pins */ LOG_ERR("SPI pinctrl setup failed (%d)", err);
remap = stm32_dt_pinctrl_remap_check(cfg->pinctrl_list, return err;
cfg->pinctrl_list_size);
if (remap < 0) {
return remap;
}
stm32_dt_pinctrl_remap_set((uint32_t)cfg->spi, remap);
}
stm32_dt_pinctrl_configure(cfg->pinctrl_list,
cfg->pinctrl_list_size);
} }
#ifdef CONFIG_SPI_STM32_INTERRUPT #ifdef CONFIG_SPI_STM32_INTERRUPT