drivers: pwm: gd32: initial version
Initial version of a PWM driver for GigaDevice GD32 SoCs. Only PWM output is supported for now (no capture support). Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas
Maureen Helm
parent
13da22e5aa
commit
0cb9a1b4cb
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@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_NPCX pwm_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XLNX_AXI_TIMER pwm_xlnx_axi_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_PWT pwm_mcux_pwt.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_GECKO pwm_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_GD32 pwm_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c)
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@ -69,4 +69,6 @@ source "drivers/pwm/Kconfig.mcux_pwt"
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source "drivers/pwm/Kconfig.gecko"
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source "drivers/pwm/Kconfig.gd32"
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endif # PWM
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11
drivers/pwm/Kconfig.gd32
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11
drivers/pwm/Kconfig.gd32
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@ -0,0 +1,11 @@
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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_GD_GD32_PWM := gd,gd32-pwm
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config PWM_GD32
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bool "GigaDevice GD32 PWM driver"
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depends on SOC_FAMILY_GD32
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default $(dt_compat_enabled,$(DT_COMPAT_GD_GD32_PWM))
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help
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Enable the GigaDevice GD32 PWM driver.
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290
drivers/pwm/pwm_gd32.c
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290
drivers/pwm/pwm_gd32.c
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@ -0,0 +1,290 @@
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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_pwm
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#include <errno.h>
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#include <drivers/pwm.h>
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#include <drivers/pinctrl.h>
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#include <soc.h>
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#include <sys/util_macro.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_gd32, CONFIG_PWM_LOG_LEVEL);
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/** PWM data. */
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struct pwm_gd32_data {
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/** Timer clock (Hz). */
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uint32_t tim_clk;
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};
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/** PWM configuration. */
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struct pwm_gd32_config {
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/** Timer register. */
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uint32_t reg;
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/** Number of channels */
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uint8_t channels;
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/** Flag to indicate if timer has 32-bit counter */
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bool is_32bit;
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/** Flag to indicate if timer is advanced */
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bool is_advanced;
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/** Prescaler. */
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uint16_t prescaler;
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/** RCU peripheral clock. */
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uint32_t rcu_periph_clock;
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/** RCU peripheral reset. */
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uint32_t rcu_periph_reset;
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/** pinctrl configurations. */
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const struct pinctrl_dev_config *pcfg;
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};
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/** Obtain channel enable bit for the given channel */
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#define TIMER_CHCTL2_CHXEN(ch) BIT(4U * (ch))
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/** Obtain polarity bit for the given channel */
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#define TIMER_CHCTL2_CHXP(ch) BIT(1U + (4U * (ch)))
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/** Obtain CHCTL0/1 mask for the given channel (0 or 1) */
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#define TIMER_CHCTLX_MSK(ch) (0xFU << (8U * (ch)))
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/** Obtain RCU register offset from RCU clock value */
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#define RCU_CLOCK_OFFSET(rcu_clock) ((rcu_clock) >> 6U)
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/**
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* Obtain the timer clock.
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*
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* @param dev Device instance.
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*
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* @return Timer clock (Hz).
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*/
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static uint32_t pwm_gd32_get_tim_clk(const struct device *dev)
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{
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const struct pwm_gd32_config *config = dev->config;
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uint32_t apb_psc, apb_clk;
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/* obtain APB prescaler value */
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if (RCU_CLOCK_OFFSET(config->rcu_periph_clock) == APB1EN_REG_OFFSET) {
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apb_psc = RCU_CFG0 & RCU_CFG0_APB1PSC;
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} else {
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apb_psc = RCU_CFG0 & RCU_CFG0_APB2PSC;
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}
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switch (apb_psc) {
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case RCU_APB1_CKAHB_DIV2:
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apb_psc = 2U;
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break;
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case RCU_APB1_CKAHB_DIV4:
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apb_psc = 4U;
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break;
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case RCU_APB1_CKAHB_DIV8:
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apb_psc = 8U;
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break;
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case RCU_APB1_CKAHB_DIV16:
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apb_psc = 16U;
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break;
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default:
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apb_psc = 1U;
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break;
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}
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apb_clk = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / apb_psc;
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#ifdef RCU_CFG1_TIMERSEL
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/*
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* The TIMERSEL bit in RCU_CFG1 controls the clock frequency of all the
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* timers connected to the APB1 and APB2 domains.
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*
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* Up to a certain threshold value of APB{1,2} prescaler, timer clock
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* equals to CK_AHB. This threshold value depends on TIMERSEL setting
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* (2 if TIMERSEL=0, 4 if TIMERSEL=1). Above threshold, timer clock is
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* set to a multiple of the APB domain clock CK_APB{1,2} (2 if
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* TIMERSEL=0, 4 if TIMERSEL=1).
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*/
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/* TIMERSEL = 0 */
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if ((RCU_CFG1 & RCU_CFG1_TIMERSEL) == 0U) {
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if (apb_psc <= 2U) {
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return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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}
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return apb_clk * 2U;
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}
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/* TIMERSEL = 1 */
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if (apb_psc <= 4U) {
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return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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}
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return apb_clk * 4U;
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#else
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/*
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* If the APB prescaler equals 1, the timer clock frequencies are set to
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* the same frequency as that of the APB domain. Otherwise, they are set
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* to twice the frequency of the APB domain.
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*/
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if (apb_psc == 1U) {
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return apb_clk;
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}
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return apb_clk * 2U;
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#endif /* RCU_CFG1_TIMERSEL */
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}
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static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_gd32_config *config = dev->config;
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if (pwm >= config->channels) {
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return -EINVAL;
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}
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if (pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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/* 16-bit timers can count up to UINT16_MAX */
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if (!config->is_32bit && (period_cycles > UINT16_MAX)) {
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return -ENOTSUP;
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}
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/* disable channel output if period is zero */
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if (period_cycles == 0U) {
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TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(pwm);
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return 0;
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}
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/* update polarity */
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if ((flags & PWM_POLARITY_INVERTED) != 0U) {
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TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(pwm);
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} else {
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TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(pwm);
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}
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/* update pulse */
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switch (pwm) {
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case 0U:
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TIMER_CH0CV(config->reg) = pulse_cycles;
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break;
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case 1U:
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TIMER_CH1CV(config->reg) = pulse_cycles;
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break;
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case 2U:
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TIMER_CH2CV(config->reg) = pulse_cycles;
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break;
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case 3U:
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TIMER_CH3CV(config->reg) = pulse_cycles;
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break;
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default:
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__ASSERT_NO_MSG(NULL);
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break;
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}
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/* update period */
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TIMER_CAR(config->reg) = period_cycles;
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/* channel not enabled: configure it */
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if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(pwm)) == 0U) {
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volatile uint32_t *chctl;
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/* select PWM1 mode, enable OC shadowing */
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if (pwm < 2U) {
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chctl = &TIMER_CHCTL0(config->reg);
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} else {
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chctl = &TIMER_CHCTL1(config->reg);
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}
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*chctl &= ~TIMER_CHCTLX_MSK(pwm);
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*chctl |= (TIMER_OC_MODE_PWM1 | TIMER_OC_SHADOW_ENABLE) <<
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(8U * (pwm % 2U));
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/* enable channel output */
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TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(pwm);
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/* generate update event (to load shadow values) */
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TIMER_SWEVG(config->reg) |= TIMER_SWEVG_UPG;
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}
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return 0;
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}
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static int pwm_gd32_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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struct pwm_gd32_data *data = dev->data;
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const struct pwm_gd32_config *config = dev->config;
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*cycles = (uint64_t)(data->tim_clk / (config->prescaler + 1U));
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return 0;
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}
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static const struct pwm_driver_api pwm_gd32_driver_api = {
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.pin_set = pwm_gd32_pin_set,
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.get_cycles_per_sec = pwm_gd32_get_cycles_per_sec,
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};
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static int pwm_gd32_init(const struct device *dev)
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{
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const struct pwm_gd32_config *config = dev->config;
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struct pwm_gd32_data *data = dev->data;
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int ret;
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rcu_periph_clock_enable(config->rcu_periph_clock);
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/* reset timer to its default state */
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rcu_periph_reset_enable(config->rcu_periph_reset);
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rcu_periph_reset_disable(config->rcu_periph_reset);
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/* apply pin configuration */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* cache timer clock value */
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data->tim_clk = pwm_gd32_get_tim_clk(dev);
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/* basic timer operation: edge aligned, up counting, shadowed CAR */
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TIMER_CTL0(config->reg) = TIMER_CKDIV_DIV1 | TIMER_COUNTER_EDGE |
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TIMER_COUNTER_UP | TIMER_CTL0_ARSE;
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TIMER_PSC(config->reg) = config->prescaler;
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/* enable primary output for advanced timers */
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if (config->is_advanced) {
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TIMER_CCHP(config->reg) |= TIMER_CCHP_POEN;
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}
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/* enable timer counter */
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TIMER_CTL0(config->reg) |= TIMER_CTL0_CEN;
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return 0;
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}
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#define PWM_GD32_DEFINE(i) \
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static struct pwm_gd32_data pwm_gd32_data_##i; \
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\
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PINCTRL_DT_INST_DEFINE(i); \
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\
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static const struct pwm_gd32_config pwm_gd32_config_##i = { \
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.reg = DT_REG_ADDR(DT_INST_PARENT(i)), \
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.rcu_periph_clock = DT_PROP(DT_INST_PARENT(i), \
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rcu_periph_clock), \
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.rcu_periph_reset = DT_PROP(DT_INST_PARENT(i), \
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rcu_periph_reset), \
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.prescaler = DT_PROP(DT_INST_PARENT(i), prescaler), \
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.channels = DT_PROP(DT_INST_PARENT(i), channels), \
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.is_32bit = DT_PROP(DT_INST_PARENT(i), is_32bit), \
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.is_advanced = DT_PROP(DT_INST_PARENT(i), is_advanced), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(i, &pwm_gd32_init, NULL, &pwm_gd32_data_##i, \
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&pwm_gd32_config_##i, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&pwm_gd32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_GD32_DEFINE)
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