drivers: counter: Fix Smartbond counter get_rate
When timer calibration for SmartBond(tm) was added, opaque type clock_control_subsystem_t that used to have device tree ordinal number was changed to enum to allow values that are not in device tree (like no clock selection). During this process counter driver for SmartBond(tm) was not updated accordingly, resulting in wrong frequency being reported to counter driver. Failure could be seen when samples/drivers/counter/alarm was execute on da1469x_dk_pro board. With this fix counter driver uses correct type when clock_control_get_rate is called and counter test works again. Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
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@ -7,7 +7,7 @@
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#define DT_DRV_COMPAT renesas_smartbond_timer
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/atomic.h>
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@ -225,7 +225,7 @@ static int counter_smartbond_init_timer(const struct device *dev)
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TIMER_Type *timer0 = ((TIMER_Type *)cfg->timer) == TIMER ? TIMER : NULL;
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const struct device *osc_dev;
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uint32_t osc_freq;
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uint32_t osc;
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enum smartbond_clock osc;
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if (cfg->clock_src_divn) {
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/* Timer clock source is DIVn 32MHz */
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@ -238,17 +238,17 @@ static int counter_smartbond_init_timer(const struct device *dev)
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switch ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) {
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case LP_CLK_OSC_RC32K:
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osc = DT_DEP_ORD(DT_NODELABEL(rc32k));
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osc = SMARTBOND_CLK_RC32K;
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break;
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case LP_CLK_OSC_RCX:
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osc = DT_DEP_ORD(DT_NODELABEL(rcx));
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osc = SMARTBOND_CLK_RCX;
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break;
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default:
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case LP_CLK_OSC_XTAL32K:
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osc = DT_DEP_ORD(DT_NODELABEL(xtal32k));
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osc = SMARTBOND_CLK_XTAL32K;
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break;
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}
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clock_control_get_rate(osc_dev, (clock_control_subsys_t *)&osc, &osc_freq);
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clock_control_get_rate(osc_dev, (clock_control_subsys_t)osc, &osc_freq);
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data->freq = osc_freq / (cfg->prescaler + 1);
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}
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timer->TIMER2_PRESCALER_REG = cfg->prescaler;
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