From 0e6aee34791c4438b11fcc9514b8a4be50985a79 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 7 Oct 2022 12:31:10 -0700 Subject: [PATCH] tests/boards/intel_adsp: Add cache related tests Tests that exercise z_xtensa_cache_[flush|inv|flush_inv]_all() functions. These tests are at board level because what is mapped into memory is SoC/board dependent - no one wants side effects due writing to some inappropriate address. Signed-off-by: Ederson de Souza --- tests/boards/intel_adsp/cache/CMakeLists.txt | 7 +++ tests/boards/intel_adsp/cache/prj.conf | 2 + tests/boards/intel_adsp/cache/src/main.c | 63 ++++++++++++++++++++ tests/boards/intel_adsp/cache/testcase.yaml | 5 ++ 4 files changed, 77 insertions(+) create mode 100644 tests/boards/intel_adsp/cache/CMakeLists.txt create mode 100644 tests/boards/intel_adsp/cache/prj.conf create mode 100644 tests/boards/intel_adsp/cache/src/main.c create mode 100644 tests/boards/intel_adsp/cache/testcase.yaml diff --git a/tests/boards/intel_adsp/cache/CMakeLists.txt b/tests/boards/intel_adsp/cache/CMakeLists.txt new file mode 100644 index 0000000000..bc96d0401b --- /dev/null +++ b/tests/boards/intel_adsp/cache/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(adsp_cache) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/boards/intel_adsp/cache/prj.conf b/tests/boards/intel_adsp/cache/prj.conf new file mode 100644 index 0000000000..9228251051 --- /dev/null +++ b/tests/boards/intel_adsp/cache/prj.conf @@ -0,0 +1,2 @@ +CONFIG_ZTEST=y +CONFIG_ZTEST_NEW_API=y diff --git a/tests/boards/intel_adsp/cache/src/main.c b/tests/boards/intel_adsp/cache/src/main.c new file mode 100644 index 0000000000..5ad4e89e3e --- /dev/null +++ b/tests/boards/intel_adsp/cache/src/main.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +ZTEST(adsp_cache, test_adsp_cache_flush_inv_all) +{ + uint32_t *cached, *uncached; + + cached = (uint32_t *)LP_SRAM_BASE; + uncached = arch_xtensa_uncached_ptr(cached); + + *cached = 42; + *uncached = 40; + + /* Just some sanity checks */ + zassert_equal(*cached, 42, NULL); + zassert_equal(*uncached, 40, NULL); + + z_xtensa_cache_flush_inv_all(); + + /* After z_xtensa_cache_flush_inv_all(), uncached should be updated */ + zassert_equal(*cached, 42, NULL); + zassert_equal(*uncached, 42, NULL); + + /* Flush and invalidate again, this time to check the invalidate part */ + z_xtensa_cache_flush_inv_all(); + *uncached = 80; + + /* As cache is invalid, cached should be updated with uncached new value */ + zassert_equal(*cached, 80, NULL); + zassert_equal(*uncached, 80, NULL); + + *cached = 82; + + /* Only cached should have changed */ + zassert_equal(*cached, 82, NULL); + zassert_equal(*uncached, 80, NULL); + + z_xtensa_cache_flush_all(); + + /* After z_xtensa_cache_flush_all(), uncached should be updated */ + zassert_equal(*cached, 82, NULL); + zassert_equal(*uncached, 82, NULL); + + *uncached = 100; + + /* As cache is not invalid, only uncached should be updated */ + zassert_equal(*cached, 82, NULL); + zassert_equal(*uncached, 100, NULL); + + z_xtensa_cache_inv_all(); + + /* Now, cached should be updated */ + zassert_equal(*cached, 100, NULL); + zassert_equal(*uncached, 100, NULL); +} + +ZTEST_SUITE(adsp_cache, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/boards/intel_adsp/cache/testcase.yaml b/tests/boards/intel_adsp/cache/testcase.yaml new file mode 100644 index 0000000000..feaa1edbe9 --- /dev/null +++ b/tests/boards/intel_adsp/cache/testcase.yaml @@ -0,0 +1,5 @@ +common: + tags: boards +tests: + boards.intel_adsp.cache: + platform_allow: intel_adsp_cavs15 intel_adsp_cavs18 intel_adsp_cavs25