dts: x86: intel: alder_lake: Added UARTs DMA instances
Added UARTs DMA instances to enable Async operations on ADL platform Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
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0018204091
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0e87de0a10
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@ -46,4 +46,16 @@ config SHELL_STACK_SIZE
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endif # SHELL
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endif # SHELL
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endif # ACPI
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endif # ACPI
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if DMA
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config DMA_64BIT
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default y
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config DMA_DW_HW_LLI
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default n
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config DMA_DW_CHANNEL_COUNT
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default 2
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endif
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config UART_NS16550_INTEL_LPSS_DMA
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default y
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endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000
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endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000
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@ -23,7 +23,3 @@
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&uart0 {
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&uart0 {
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status = "okay";
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status = "okay";
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};
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};
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&uart1 {
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status = "okay";
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};
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@ -78,6 +78,12 @@
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status = "disabled";
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status = "disabled";
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};
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};
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uart1_dma: uart1_dma {
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compatible = "intel,lpss";
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#dma-cells = <1>;
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status = "disabled";
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};
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uart1: uart1 {
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uart1: uart1 {
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compatible = "ns16550";
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compatible = "ns16550";
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vendor-id = <0x8086>;
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vendor-id = <0x8086>;
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@ -87,6 +93,14 @@
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reg-shift = <2>;
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reg-shift = <2>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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dmas = <&uart1_dma 0>, <&uart1_dma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart2_dma: uart2_dma {
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compatible = "intel,lpss";
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#dma-cells = <1>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -99,6 +113,8 @@
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reg-shift = <2>;
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reg-shift = <2>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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dmas = <&uart2_dma 0>, <&uart2_dma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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status = "disabled";
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};
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};
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