xtensa: polish doxygen and add to missing doc
This polishes doxygen to, hopefully, make it better looking on the API doc. Also adds missing doc to various functions and macros. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
035c8d8ceb
commit
0ee1e28a2f
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@ -7,7 +7,7 @@
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* @file
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* @brief Xtensa specific kernel interface header
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* This header contains the Xtensa specific kernel interface. It is included
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* by the generic kernel interface header (include/arch/cpu.h)
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* by the generic kernel interface header (include/zephyr/arch/cpu.h)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_H_
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@ -33,6 +33,8 @@
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#include <zephyr/arch/xtensa/thread_stack.h>
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#include <zephyr/sys/slist.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/arch/xtensa/xtensa_mmu.h>
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/**
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@ -61,7 +63,23 @@ struct arch_mem_domain {
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sys_snode_t node;
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};
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/**
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* @brief Generate hardware exception.
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*
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* This generates hardware exception which is used by ARCH_EXCEPT().
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*
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* @param reason_p Reason for exception.
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*/
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extern void xtensa_arch_except(int reason_p);
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/**
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* @brief Generate kernel oops.
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*
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* This generates kernel oops which is used by arch_syscall_oops().
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*
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* @param reason_p Reason for exception.
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* @param ssf Stack pointer.
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*/
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extern void xtensa_arch_kernel_oops(int reason_p, void *ssf);
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#ifdef CONFIG_USERSPACE
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@ -79,9 +97,9 @@ extern void xtensa_arch_kernel_oops(int reason_p, void *ssf);
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#else
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#define ARCH_EXCEPT(reason_p) do { \
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xtensa_arch_except(reason_p); \
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CODE_UNREACHABLE; \
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} while (false)
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xtensa_arch_except(reason_p); \
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CODE_UNREACHABLE; \
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} while (false)
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#endif
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@ -93,44 +111,47 @@ __syscall void xtensa_user_fault(unsigned int reason);
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extern void z_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
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#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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{ \
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Z_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
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}
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extern uint32_t sys_clock_cycle_get_32(void);
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{ \
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Z_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
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}
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/** Implementation of @ref arch_k_cycle_get_32. */
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return sys_clock_cycle_get_32();
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}
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extern uint64_t sys_clock_cycle_get_64(void);
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/** Implementation of @ref arch_k_cycle_get_64. */
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static inline uint64_t arch_k_cycle_get_64(void)
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{
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return sys_clock_cycle_get_64();
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}
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/** Implementation of @ref arch_nop. */
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static ALWAYS_INLINE void arch_nop(void)
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{
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__asm__ volatile("nop");
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}
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/**
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* @brief Lock VECBASE if supported by hardware.
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*
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* The bit 0 of VECBASE acts as a lock bit on hardware supporting
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* this feature. When this bit is set, VECBASE cannot be changed
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* until it is cleared by hardware reset. When the hardware does not
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* support this bit, it is hardwired to 0.
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*/
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static ALWAYS_INLINE void xtensa_vecbase_lock(void)
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{
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int vecbase;
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__asm__ volatile("rsr.vecbase %0" : "=r" (vecbase));
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/* In some targets the bit 0 of VECBASE works as lock bit.
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* When this bit set, VECBASE can't be changed until it is cleared by
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* reset. When the target does not have it, it is hardwired to 0.
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**/
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__asm__ volatile("wsr.vecbase %0; rsync" : : "r" (vecbase | 1));
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}
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#if defined(CONFIG_XTENSA_RPO_CACHE)
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#if defined(CONFIG_ARCH_HAS_COHERENCE)
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#if defined(CONFIG_XTENSA_RPO_CACHE) || defined(__DOXYGEN__)
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#if defined(CONFIG_ARCH_HAS_COHERENCE) || defined(__DOXYGEN__)
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/** Implementation of @ref arch_mem_coherent. */
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static inline bool arch_mem_coherent(void *ptr)
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{
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size_t addr = (size_t) ptr;
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@ -139,6 +160,19 @@ static inline bool arch_mem_coherent(void *ptr)
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}
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#endif
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/**
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* @brief Test if a pointer is in cached region.
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*
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* Some hardware may map the same physical memory twice
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* so that it can be seen in both (incoherent) cached mappings
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* and a coherent "shared" area. This tests if a particular
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* pointer is within the cached, coherent area.
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*
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* @param ptr Pointer
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*
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* @retval True if pointer is in cached region.
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* @retval False if pointer is not in cached region.
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*/
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static inline bool arch_xtensa_is_ptr_cached(void *ptr)
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{
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size_t addr = (size_t) ptr;
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@ -146,6 +180,19 @@ static inline bool arch_xtensa_is_ptr_cached(void *ptr)
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return (addr >> 29) == CONFIG_XTENSA_CACHED_REGION;
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}
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/**
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* @brief Test if a pointer is in un-cached region.
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*
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* Some hardware may map the same physical memory twice
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* so that it can be seen in both (incoherent) cached mappings
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* and a coherent "shared" area. This tests if a particular
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* pointer is within the un-cached, incoherent area.
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*
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* @param ptr Pointer
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*
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* @retval True if pointer is not in cached region.
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* @retval False if pointer is in cached region.
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*/
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static inline bool arch_xtensa_is_ptr_uncached(void *ptr)
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{
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size_t addr = (size_t) ptr;
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@ -173,6 +220,7 @@ static ALWAYS_INLINE uint32_t z_xtrpoflip(uint32_t addr, uint32_t rto, uint32_t
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return (addr & ~(7U << 29)) | rto;
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}
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}
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/**
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* @brief Return cached pointer to a RAM address
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*
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@ -271,10 +319,14 @@ static inline void *arch_xtensa_uncached_ptr(void __sparse_cache *ptr)
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addr += addrincr; \
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} while (0)
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#define ARCH_XTENSA_SET_RPO_TLB() do { \
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register uint32_t addr = 0, addrincr = 0x20000000; \
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FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7); \
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} while (0)
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/**
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* @brief Setup RPO TLB registers.
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*/
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#define ARCH_XTENSA_SET_RPO_TLB() \
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do { \
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register uint32_t addr = 0, addrincr = 0x20000000; \
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FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7); \
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} while (0)
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#else /* CONFIG_XTENSA_RPO_CACHE */
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@ -304,7 +356,17 @@ static inline void *arch_xtensa_uncached_ptr(void *ptr)
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#endif /* CONFIG_XTENSA_RPO_CACHE */
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#ifdef CONFIG_XTENSA_MMU
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#if defined(CONFIG_XTENSA_MMU) || defined(__DOXYGEN__)
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/**
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* @brief Peform additional steps after MMU initialization.
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*
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* This performs additional steps related to memory management
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* after the main MMU initialization code. This needs to defined
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* in the SoC layer. Default is do no nothing.
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*
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* @param is_core0 True if this is called while executing on
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* CPU core #0.
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*/
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extern void arch_xtensa_mmu_post_init(bool is_core0);
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#endif
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@ -13,26 +13,53 @@
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#include <zephyr/kernel_structs.h>
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#include <zsr.h>
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/**
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* @brief Read a special register.
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*
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* @param sr Name of special register.
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*
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* @return Value of special register.
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*/
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#define XTENSA_RSR(sr) \
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({uint32_t v; \
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__asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
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v; })
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/**
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* @brief Write to a special register.
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*
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* @param sr Name of special register.
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* @param v Value to be written to special register.
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*/
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#define XTENSA_WSR(sr, v) \
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do { \
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__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
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} while (false)
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/**
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* @brief Read a user register.
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*
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* @param ur Name of user register.
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*
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* @return Value of user register.
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*/
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#define XTENSA_RUR(ur) \
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({uint32_t v; \
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__asm__ volatile ("rur." ur " %0" : "=a"(v)); \
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v; })
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/**
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* @brief Write to a user register.
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*
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* @param ur Name of user register.
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* @param v Value to be written to user register.
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*/
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#define XTENSA_WUR(ur, v) \
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do { \
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__asm__ volatile ("wur." ur " %0" : : "r"(v)); \
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} while (false)
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/** Implementation of @ref arch_curr_cpu. */
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static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
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{
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_cpu_t *cpu;
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@ -42,6 +69,7 @@ static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
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return cpu;
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}
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/** Implementation of @ref arch_proc_id. */
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static ALWAYS_INLINE uint32_t arch_proc_id(void)
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{
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uint32_t prid;
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@ -54,6 +82,7 @@ static ALWAYS_INLINE uint32_t arch_proc_id(void)
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extern unsigned int soc_num_cpus;
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#endif
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/** Implementation of @ref arch_num_cpus. */
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static ALWAYS_INLINE unsigned int arch_num_cpus(void)
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{
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#ifdef CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
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@ -1,11 +1,12 @@
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/**
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/*
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* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ATOMIC_XTENSA_H_
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#define ZEPHYR_INCLUDE_ATOMIC_XTENSA_H_
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/* Included from <sys/atomic.h> */
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/* Included from <zephyr/sys/atomic.h> */
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/* Recent GCC versions actually do have working atomics support on
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* Xtensa (and so should work with CONFIG_ATOMIC_OPERATIONS_BUILTIN),
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@ -13,6 +14,7 @@
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* inline implementation here that is more or less identical
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*/
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/** Implementation of @ref atomic_get. */
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static ALWAYS_INLINE atomic_val_t atomic_get(const atomic_t *target)
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{
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atomic_val_t ret;
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@ -28,6 +30,23 @@ static ALWAYS_INLINE atomic_val_t atomic_get(const atomic_t *target)
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return ret;
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}
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/**
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* @brief Xtensa specific atomic compare-and-set (CAS).
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*
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* @param addr Address of atomic variable.
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* @param oldval Original value to compare against.
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* @param newval New value to store.
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*
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* This utilizes SCOMPARE1 register and s32c1i instruction to
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* perform compare-and-set atomic operation. This will
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* unconditionally read from the atomic variable at @p addr
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* before the comparison. This value is returned from
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* the function.
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*
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* @return The value at the memory location before CAS.
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*
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* @see atomic_cas.
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*/
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static ALWAYS_INLINE
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atomic_val_t xtensa_cas(atomic_t *addr, atomic_val_t oldval,
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atomic_val_t newval)
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@ -38,12 +57,14 @@ atomic_val_t xtensa_cas(atomic_t *addr, atomic_val_t oldval,
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return newval; /* got swapped with the old memory by s32c1i */
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}
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/** Implementation of @ref atomic_cas. */
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static ALWAYS_INLINE
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bool atomic_cas(atomic_t *target, atomic_val_t oldval, atomic_val_t newval)
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{
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return oldval == xtensa_cas(target, oldval, newval);
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}
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/** Implementation of @ref atomic_ptr_cas. */
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static ALWAYS_INLINE
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bool atomic_ptr_cas(atomic_ptr_t *target, void *oldval, void *newval)
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{
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@ -57,7 +78,6 @@ bool atomic_ptr_cas(atomic_ptr_t *target, void *oldval, void *newval)
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* specified expression. Evaluates to the old value which was
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* atomically replaced.
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*/
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#define Z__GEN_ATOMXCHG(expr) ({ \
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atomic_val_t res, cur; \
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do { \
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@ -66,75 +86,88 @@ bool atomic_ptr_cas(atomic_ptr_t *target, void *oldval, void *newval)
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} while (res != cur); \
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res; })
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/** Implementation of @ref atomic_set. */
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static ALWAYS_INLINE
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atomic_val_t atomic_set(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(value);
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}
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/** Implementation of @ref atomic_add. */
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static ALWAYS_INLINE
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atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur + value);
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}
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/** Implementation of @ref atomic_sub. */
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static ALWAYS_INLINE
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atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur - value);
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}
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/** Implementation of @ref atomic_inc. */
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static ALWAYS_INLINE
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atomic_val_t atomic_inc(atomic_t *target)
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{
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return Z__GEN_ATOMXCHG(cur + 1);
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}
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/** Implementation of @ref atomic_dec. */
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static ALWAYS_INLINE
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atomic_val_t atomic_dec(atomic_t *target)
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{
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return Z__GEN_ATOMXCHG(cur - 1);
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}
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/** Implementation of @ref atomic_or. */
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static ALWAYS_INLINE atomic_val_t atomic_or(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur | value);
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}
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/** Implementation of @ref atomic_xor. */
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static ALWAYS_INLINE atomic_val_t atomic_xor(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur ^ value);
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}
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/** Implementation of @ref atomic_and. */
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static ALWAYS_INLINE atomic_val_t atomic_and(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur & value);
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}
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/** Implementation of @ref atomic_nand. */
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static ALWAYS_INLINE atomic_val_t atomic_nand(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(~(cur & value));
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}
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/** Implementation of @ref atomic_ptr_get. */
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static ALWAYS_INLINE void *atomic_ptr_get(const atomic_ptr_t *target)
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{
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return (void *) atomic_get((atomic_t *)target);
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}
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/** Implementation of @ref atomic_ptr_set. */
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static ALWAYS_INLINE void *atomic_ptr_set(atomic_ptr_t *target, void *value)
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{
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return (void *) atomic_set((atomic_t *) target, (atomic_val_t) value);
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}
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/** Implementation of @ref atomic_clear. */
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static ALWAYS_INLINE atomic_val_t atomic_clear(atomic_t *target)
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{
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return atomic_set(target, 0);
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}
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/** Implementation of @ref atomic_ptr_clear. */
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static ALWAYS_INLINE void *atomic_ptr_clear(atomic_ptr_t *target)
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{
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return (void *) atomic_set((atomic_t *) target, 0);
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@ -22,7 +22,9 @@ BUILD_ASSERT(Z_IS_POW2(XCHAL_DCACHE_LINESIZE));
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BUILD_ASSERT(Z_IS_POW2(Z_DCACHE_MAX));
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#endif
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#if defined(CONFIG_DCACHE)
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#if defined(CONFIG_DCACHE) || defined(__DOXYGEN__)
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/** Implementation of @ref arch_dcache_flush_range. */
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static ALWAYS_INLINE int arch_dcache_flush_range(void *addr, size_t bytes)
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{
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#if XCHAL_DCACHE_SIZE
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@ -38,6 +40,7 @@ static ALWAYS_INLINE int arch_dcache_flush_range(void *addr, size_t bytes)
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return 0;
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}
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/** Implementation of @ref arch_dcache_flush_and_invd_range. */
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static ALWAYS_INLINE int arch_dcache_flush_and_invd_range(void *addr, size_t bytes)
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{
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#if XCHAL_DCACHE_SIZE
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|
|
@ -53,6 +56,7 @@ static ALWAYS_INLINE int arch_dcache_flush_and_invd_range(void *addr, size_t byt
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_invd_range. */
|
||||
static ALWAYS_INLINE int arch_dcache_invd_range(void *addr, size_t bytes)
|
||||
{
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
|
|
@ -68,6 +72,7 @@ static ALWAYS_INLINE int arch_dcache_invd_range(void *addr, size_t bytes)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_invd_all. */
|
||||
static ALWAYS_INLINE int arch_dcache_invd_all(void)
|
||||
{
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
|
|
@ -81,6 +86,7 @@ static ALWAYS_INLINE int arch_dcache_invd_all(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_flush_all. */
|
||||
static ALWAYS_INLINE int arch_dcache_flush_all(void)
|
||||
{
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
|
|
@ -94,6 +100,7 @@ static ALWAYS_INLINE int arch_dcache_flush_all(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_flush_and_invd_all. */
|
||||
static ALWAYS_INLINE int arch_dcache_flush_and_invd_all(void)
|
||||
{
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
|
|
@ -107,11 +114,13 @@ static ALWAYS_INLINE int arch_dcache_flush_and_invd_all(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_enable. */
|
||||
static ALWAYS_INLINE void arch_dcache_enable(void)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_dcache_disable. */
|
||||
static ALWAYS_INLINE void arch_dcache_disable(void)
|
||||
{
|
||||
/* nothing */
|
||||
|
|
@ -119,18 +128,21 @@ static ALWAYS_INLINE void arch_dcache_disable(void)
|
|||
|
||||
#endif /* CONFIG_DCACHE */
|
||||
|
||||
#if defined(CONFIG_ICACHE)
|
||||
#if defined(CONFIG_ICACHE) || defined(__DOXYGEN__)
|
||||
|
||||
/** Implementation of @ref arch_icache_line_size_get. */
|
||||
static ALWAYS_INLINE size_t arch_icache_line_size_get(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_flush_all. */
|
||||
static ALWAYS_INLINE int arch_icache_flush_all(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_invd_all. */
|
||||
static ALWAYS_INLINE int arch_icache_invd_all(void)
|
||||
{
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
|
|
@ -139,16 +151,19 @@ static ALWAYS_INLINE int arch_icache_invd_all(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_flush_and_invd_all. */
|
||||
static ALWAYS_INLINE int arch_icache_flush_and_invd_all(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_flush_range. */
|
||||
static ALWAYS_INLINE int arch_icache_flush_range(void *addr, size_t size)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_invd_range. */
|
||||
static ALWAYS_INLINE int arch_icache_invd_range(void *addr, size_t size)
|
||||
{
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
|
|
@ -157,16 +172,19 @@ static ALWAYS_INLINE int arch_icache_invd_range(void *addr, size_t size)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_flush_and_invd_range. */
|
||||
static ALWAYS_INLINE int arch_icache_flush_and_invd_range(void *addr, size_t size)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_enable. */
|
||||
static ALWAYS_INLINE void arch_icache_enable(void)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_icache_disable. */
|
||||
static ALWAYS_INLINE void arch_icache_disable(void)
|
||||
{
|
||||
/* nothing */
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@
|
|||
#define XTREG_GRP_SPECIAL 0x0200
|
||||
#define XTREG_GRP_USER 0x0300
|
||||
|
||||
/*
|
||||
* Register description fot GDB stub.
|
||||
/**
|
||||
* @brief Register description for GDB stub.
|
||||
*
|
||||
* Values are based on gdb/gdb/xtensa-config.c in the Xtensa overlay,
|
||||
* where registers are defined using XTREG() macro:
|
||||
|
|
@ -35,32 +35,35 @@
|
|||
* gpkt_offset : ofs
|
||||
*/
|
||||
struct xtensa_register {
|
||||
/* Register value */
|
||||
/** Register value */
|
||||
uint32_t val;
|
||||
|
||||
/* GDB register index (for p/P packets) */
|
||||
/** GDB register index (for p/P packets) */
|
||||
uint8_t idx;
|
||||
|
||||
/* Size of register */
|
||||
/** Size of register */
|
||||
uint8_t byte_size;
|
||||
|
||||
/* Xtensa register number */
|
||||
/** Xtensa register number */
|
||||
uint16_t regno;
|
||||
|
||||
/* Offset of this register in GDB G-packet.
|
||||
/**
|
||||
* Offset of this register in GDB G-packet.
|
||||
* -1 if register is not in G-packet.
|
||||
*/
|
||||
int16_t gpkt_offset;
|
||||
|
||||
/* Offset of saved register in stack frame.
|
||||
/**
|
||||
* Offset of saved register in stack frame.
|
||||
* 0 if not saved in stack frame.
|
||||
*/
|
||||
int8_t stack_offset;
|
||||
|
||||
/* Sequence number */
|
||||
/** Sequence number */
|
||||
uint8_t seqno;
|
||||
|
||||
/* Set 1 to if register should not be written
|
||||
/**
|
||||
* Set to 1 if register should not be written
|
||||
* to during debugging.
|
||||
*/
|
||||
uint8_t is_read_only:1;
|
||||
|
|
@ -78,26 +81,29 @@ struct xtensa_register {
|
|||
*/
|
||||
#include <gdbstub/soc.h>
|
||||
|
||||
/**
|
||||
* @brief Architecture specific GDB context.
|
||||
*/
|
||||
struct gdb_ctx {
|
||||
/* Exception reason */
|
||||
/** Exception reason */
|
||||
unsigned int exception;
|
||||
|
||||
/* Register descriptions */
|
||||
/** Register descriptions */
|
||||
struct xtensa_register *regs;
|
||||
|
||||
/* Number of registers */
|
||||
/** Number of registers */
|
||||
uint8_t num_regs;
|
||||
|
||||
/* Sequence number */
|
||||
/** Sequence number */
|
||||
uint8_t seqno;
|
||||
|
||||
/* Index in register descriptions of A0 register */
|
||||
/** Index in register descriptions of A0 register */
|
||||
uint8_t a0_idx;
|
||||
|
||||
/* Index in register descriptions of AR0 register */
|
||||
/** Index in register descriptions of AR0 register */
|
||||
uint8_t ar_idx;
|
||||
|
||||
/* Index in register descriptions of WINDOWBASE register */
|
||||
/** Index in register descriptions of WINDOWBASE register */
|
||||
uint8_t wb_idx;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -130,6 +130,7 @@ static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
|
|||
z_xt_ints_off(1 << irq);
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_irq_lock. */
|
||||
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
|
||||
{
|
||||
unsigned int key;
|
||||
|
|
@ -139,12 +140,14 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
|
|||
return key;
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_irq_unlock. */
|
||||
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
|
||||
{
|
||||
__asm__ volatile("wsr.ps %0; rsync"
|
||||
:: "r"(key) : "memory");
|
||||
}
|
||||
|
||||
/** Implementation of @ref arch_irq_unlocked. */
|
||||
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
|
||||
{
|
||||
return (key & 0xf) == 0; /* INTLEVEL field */
|
||||
|
|
|
|||
Loading…
Reference in a new issue