ARC: Add support for basic QEMU platform for ARC EM & HS

Now when we're finally ready to open QEMU port for ARC
we introduce the first ever platform it supports and in fact does
that quite well - Zephyr RTOS.

For now we only offer support of basic EM & HS code execution,
built-in timers, interrupt controller and set of very simple
peripherals: DW UART & optionally MMIO Virtio devices.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

boards/arc/qemu_arc/Kconfig.board

@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_ARC
+	bool "ARC QEMU for EM & HS cores"
+	depends on SOC_QEMU_ARC
+	select QEMU_TARGET

boards/arc/qemu_arc/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QEMU_ARC
+
+config BOARD
+	default "qemu_arc"
+
+endif

boards/arc/qemu_arc/board.cmake

@@ -0,0 +1,28 @@
+set(EMU_PLATFORM qemu)
+
+set(QEMU_CPU_TYPE_${ARCH} arc)
+
+if(${CONFIG_SOC_QEMU_ARC_EM})
+set(QEMU_CPU_TYPE_${ARCH} arcem)
+set(QEMU_FLAGS_${ARCH} -cpu arcem)
+elseif(${CONFIG_SOC_QEMU_ARC_HS})
+set(QEMU_CPU_TYPE_${ARCH} archs)
+set(QEMU_FLAGS_${ARCH} -cpu archs)
+endif()
+
+list(APPEND QEMU_FLAGS_${ARCH}
+  -M simhs
+  -m 8M
+  -nographic
+  -no-reboot
+  -monitor none
+  -global cpu.firq=false
+  -global cpu.num-irqlevels=15
+  -global cpu.num-irq=25
+  -global cpu.ext-irq=20
+  -global cpu.freq_hz=1000000
+  -global cpu.timer0=true
+  -global cpu.timer1=true
+  )
+
+set(BOARD_DEBUG_RUNNER qemu)

boards/arc/qemu_arc/doc/index.rst

@@ -0,0 +1,98 @@
+.. _qemu_arc:
+
+ARC EM & HS Emulation (QEMU)
+###############################
+
+Overview
+********
+
+This board configuration will use QEMU to emulate a generic ARC EM &
+ARC HS hardware platform.
+
+The following features of ARCv2 ISA cores are currently supported:
+
+* ARC EM or ARC HS core (both belong to ARCv2 ISA family still
+  they are binary incompatible)
+* Only little-endian configurations
+* Full 32 register set
+* ARC core free-running timers/counters Timer0 & Timer1
+* ARC core interrupt controller with multiple priority levels
+* DW UART
+* 5 slots for MMIO Virtio devices
+
+Hardware
+********
+Supported Features
+==================
+
+The following hardware features are supported:
+
++--------------+------------+----------------------+
+| Interface    | Controller | Driver/Component     |
++==============+============+======================+
+| ARCv2 INTC   | on-chip    | interrupt controller |
++--------------+------------+----------------------+
+| DW UART      | on-chip    | serial port          |
++--------------+------------+----------------------+
+| ARC TIMER0   | on-chip    | system clock         |
++--------------+------------+----------------------+
+
+The kernel currently does not support other hardware features on this platform.
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 1 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+DesignWare UART.
+
+Known Problems or Limitations
+==============================
+
+The following platform features are unsupported:
+
+* Memory-protection unit (MPU)
+* MMIO Virtio Ethernet
+
+Programming and Debugging
+*************************
+
+Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
+emulated environment, for example, with the :ref:`synchronization_sample`
+(note you may use ``qemu_arc_em`` or ``qemu_arc_hs`` depending on target CPU):
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: qemu_arc_em
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it using
+QEMU, and display the following console output:
+
+.. code-block:: console
+
+        *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57  ***
+        threadA: Hello World from qemu_arc!
+        threudB: Hello World from qemu_arc!
+        threadA: Hello World from qemu_arc!
+        threadB: Hello World from qemu_arc!
+
+Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+
+References
+**********
+
+1.`Programmer’s Reference Manual for ARC HS
+   <https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-HS.pdf>`_

boards/arc/qemu_arc/qemu_arc.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2020, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include "skeleton.dtsi"
+
+#define DT_FLASH_SIZE		DT_SIZE_M(4)
+#define DT_SRAM_SIZE		DT_SIZE_M(4)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	intc: arcv2-intc {
+		compatible = "snps,arcv2-intc";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	flash0: flash@80000000 {
+		compatible = "soc-nv-flash";
+		reg = <0x80000000 DT_FLASH_SIZE>;
+	};
+
+	sram0: sram@80400000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x80400000 DT_SRAM_SIZE>;
+	};
+
+	ns16550_uart: uart@f0000000 {
+		compatible = "ns16550";
+		clock-frequency = <10000000>;
+		reg = <0xf0000000 0x400>;
+		current-speed = <115200>;
+		label = "UART_0";
+		interrupt-parent = <&intc>;
+		interrupts = <24 1>;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &ns16550_uart;
+		zephyr,shell-uart = &ns16550_uart;
+	};
+};

boards/arc/qemu_arc/qemu_arc_em.dts

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "qemu_arc.dtsi"
+
+/ {
+	model = "QEMU ARC EM";
+	compatible = "qemu,arcem";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,arcem";
+			reg = <0>;
+		};
+	};
+};

boards/arc/qemu_arc/qemu_arc_em.yaml

@@ -0,0 +1,12 @@
+identifier: qemu_arc_em
+name: QEMU Emulation for ARC EM
+type: qemu
+simulation: qemu
+arch: arc
+toolchain:
+  - zephyr
+testing:
+  default: true
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/qemu_arc/qemu_arc_em_defconfig

@@ -0,0 +1,13 @@
+CONFIG_CPU_ARCEM=y
+CONFIG_SOC_QEMU_ARC=y
+CONFIG_SOC_QEMU_ARC_EM=y
+CONFIG_XIP=y
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_ARC_HAS_STACK_CHECKING=n
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y

boards/arc/qemu_arc/qemu_arc_hs.dts

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "qemu_arc.dtsi"
+
+/ {
+	model = "QEMU ARC HS";
+	compatible = "qemu,archs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+	};
+};

boards/arc/qemu_arc/qemu_arc_hs.yaml

@@ -0,0 +1,12 @@
+identifier: qemu_arc_hs
+name: QEMU Emulation for ARC HS
+type: qemu
+simulation: qemu
+arch: arc
+toolchain:
+  - zephyr
+testing:
+  default: true
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/qemu_arc/qemu_arc_hs_defconfig

@@ -0,0 +1,13 @@
+CONFIG_CPU_ARCHS=y
+CONFIG_SOC_QEMU_ARC=y
+CONFIG_SOC_QEMU_ARC_HS=y
+CONFIG_XIP=y
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_ARC_HAS_STACK_CHECKING=n
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y

soc/arc/snps_qemu/CMakeLists.txt

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)

soc/arc/snps_qemu/Kconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "ARC QEMU SoC Selection"
+	default SOC_QEMU_ARC_HS
+	depends on SOC_QEMU_ARC
+
+config SOC_QEMU_ARC_EM
+	bool "Synopsys ARC EM in QEMU"
+
+config SOC_QEMU_ARC_HS
+	bool "Synopsys ARC HS in QEMU"
+
+endchoice

soc/arc/snps_qemu/Kconfig.defconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_QEMU_ARC
+
+config SOC
+	string
+	default "snps_qemu"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 1000000
+
+config UART_CONSOLE_ON_DEV_NAME
+	string
+	default "UART_0"
+
+config RGF_NUM_BANKS
+	default 1
+
+config ARC_FIRQ
+	default n
+
+config NUM_IRQ_PRIO_LEVELS
+	default 15
+
+config NUM_IRQS
+	default 25
+
+source "soc/arc/snps_qemu/Kconfig.defconfig.em"
+
+endif

soc/arc/snps_qemu/Kconfig.defconfig.em

@@ -0,0 +1,9 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_QEMU_ARC_EM
+
+config CPU_EM4
+	default y
+
+endif

soc/arc/snps_qemu/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_ARC
+	bool "QEMU emulation of ARC cores"
+	select ARC

soc/arc/snps_qemu/linker.ld

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <devicetree.h>
+#include <autoconf.h>
+
+/*
+ * SRAM base address and size
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+#include <arch/arc/v2/linker.ld>

soc/arc/snps_qemu/soc.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief SoC configuration macros for ARC QEMU
+ *
+ * This header file is used to specify and describe SoC-level
+ * aspects for the target.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+/* ARC Core IRQs */
+#define IRQ_TIMER0			16
+#define IRQ_TIMER1			17
+
+#endif /* _SOC__H_ */