riscv: Rework and cleanup Kconfig

This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

arch/riscv/Kconfig

@@ -9,18 +9,6 @@ config ARCH
 	default "riscv64" if 64BIT
 	default "riscv32"
 
-config COMPRESSED_ISA
-	bool
-	default y if 64BIT
-
-config RISCV_ATOMICS_ISA
-	bool "RISC-V atomics 'a' extension"
-	default y
-
-config RISCV_MUL_ISA
-	bool "RISC-V HW multiply 'm' extension"
-	default y
-
 config FLOAT_HARD
 	bool "Hard-float calling convention"
 	default y
@@ -42,13 +30,6 @@ config RISCV_GP
 
 menu "RISCV Processor Options"
 
-config CORE_E31
-	bool "Use E31 core"
-	select RISCV_PMP
-	default n
-	help
-	  This option signifies the use of a core of the E31 family.
-
 config INCLUDE_RESET_VECTOR
 	bool "Include Reset vector"
 	help
@@ -207,4 +188,7 @@ config CMSIS_THREAD_MAX_STACK_SIZE
 config CMSIS_V2_THREAD_MAX_STACK_SIZE
 	default 1024 if 64BIT
 
+rsource "Kconfig.isa"
+rsource "Kconfig.core"
+
 endmenu

arch/riscv/Kconfig.core

@@ -0,0 +1,16 @@
+# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+menu "RISCV core"
+
+config RISCV_CORE_E31
+	bool "E31 core"
+	select RISCV_PMP
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	help
+	  SiFive E31 Standard Core
+
+endmenu

arch/riscv/Kconfig.isa

@@ -0,0 +1,93 @@
+# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RISCV_ISA_RV32I
+	bool
+	help
+	  RV32I Base Integer Instruction Set - 32bit
+
+config RISCV_ISA_RV32E
+	bool
+	help
+	  RV32E Base Integer Instruction Set (Embedded) - 32bit
+
+config RISCV_ISA_RV64I
+	bool
+	default y if 64BIT
+	help
+	  RV64I Base Integer Instruction Set - 64bit
+
+config RISCV_ISA_RV128I
+	bool
+	help
+	  RV128I Base Integer Instruction Set - 128bit
+
+config RISCV_ISA_EXT_M
+	bool
+	help
+	  (M) - Standard Extension for Integer Multiplication and Division
+
+	  Standard integer multiplication and division instruction extension,
+	  which is named "M" and contains instructions that multiply or divide
+	  values held in two integer registers.
+
+config RISCV_ISA_EXT_A
+	bool
+	help
+	  (A) - Standard Extension for Atomic Instructions
+
+	  The standard atomic instruction extension is denoted by instruction
+	  subset name "A", and contains instructions that atomically
+	  read-modify-write memory to support synchronization between multiple
+	  RISC-V threads running in the same memory space.
+
+config RISCV_ISA_EXT_F
+	bool
+	help
+	  (F) - Standard Extension for Single-Precision Floating-Point
+
+	  Standard instruction-set extension for single-precision
+	  floating-point, which is named "F" and adds single-precision
+	  floating-point computational instructions compliant with the IEEE
+	  754-2008 arithmetic standard.
+
+config RISCV_ISA_EXT_D
+	bool
+	depends on RISCV_ISA_EXT_F
+	help
+	  (D) - Standard Extension for Double-Precision Floating-Point
+
+	  Standard double-precision floating-point instruction-set extension,
+	  which is named "D" and adds double-precision floating-point
+	  computational instructions compliant with the IEEE 754-2008
+	  arithmetic standard.
+
+config RISCV_ISA_EXT_G
+	bool
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
+	help
+	  (MAFD) MAFD extensions
+
+config RISCV_ISA_EXT_Q
+	bool
+	depends on RISCV_ISA_RV64I
+	depends on RISCV_ISA_EXT_F
+	depends on RISCV_ISA_EXT_D
+	help
+	  (Q) - Standard Extension for Quad-Precision Floating-Point
+
+	  Standard extension for 128-bit binary floating-point instructions
+	  compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or
+	  quad-precision binary floatingpoint instruction subset is named "Q".
+
+config RISCV_ISA_EXT_C
+	bool
+	help
+	  (C) - Standard Extension for Compressed Instructions
+
+	  RISC-V standard compressed instruction set extension, named "C",
+	  which reduces static and dynamic code size by adding short 16-bit
+	  instruction encodings for common operations.

boards/riscv/hifive1_revb/hifive1_revb_defconfig

@@ -11,4 +11,4 @@ CONFIG_SERIAL=y
 CONFIG_UART_SIFIVE=y
 CONFIG_UART_SIFIVE_PORT_0=y
 CONFIG_UART_CONSOLE=y
-CONFIG_CORE_E31=y
+CONFIG_RISCV_CORE_E31=y

boards/riscv/qemu_riscv32/Kconfig.board

@@ -5,15 +5,18 @@ config BOARD_QEMU_RISCV32
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
 	select CPU_HAS_FPU
+	select RISCV_ISA_RV32I
 
 config BOARD_QEMU_RISCV32_SMP
 	bool "QEMU RISCV32 SMP target"
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
 	select CPU_HAS_FPU
+	select RISCV_ISA_RV32I
 
 config BOARD_QEMU_RISCV32_XIP
 	bool "QEMU RISCV32 XIP target"
 	depends on SOC_RISCV_SIFIVE_FREEDOM
 	select QEMU_TARGET
 	select CPU_HAS_FPU
+	select RISCV_ISA_RV32I

boards/riscv/qemu_riscv32/Kconfig.defconfig

@@ -8,9 +8,6 @@ config BOARD
 	default "qemu_riscv32_xip" if BOARD_QEMU_RISCV32_XIP
 	default "qemu_riscv32_smp" if BOARD_QEMU_RISCV32_SMP
 
-config COMPRESSED_ISA
-	default y
-
 # Use thread local storage by default so that
 # this feature gets more CI coverage.
 config THREAD_LOCAL_STORAGE

boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig

@@ -15,4 +15,4 @@ CONFIG_GPIO=y
 CONFIG_GPIO_SIFIVE=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
 CONFIG_QEMU_ICOUNT_SHIFT=6
-CONFIG_CORE_E31=y
+CONFIG_RISCV_CORE_E31=y

boards/riscv/qemu_riscv64/Kconfig.board

@@ -7,6 +7,7 @@ config BOARD_QEMU_RISCV64
 	select QEMU_TARGET
 	select 64BIT
 	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I
 
 config BOARD_QEMU_RISCV64_SMP
 	bool "QEMU RISCV64 SMP target"
@@ -14,3 +15,4 @@ config BOARD_QEMU_RISCV64_SMP
 	select QEMU_TARGET
 	select 64BIT
 	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I

boards/riscv/tlsr9518adk80d/Kconfig.defconfig

@@ -6,9 +6,6 @@ if BOARD_TLSR9518ADK80D
 config BOARD
 	default "tlsr9518adk80d"
 
-config COMPRESSED_ISA
-	default y
-
 config GPIO_TELINK_B91
 	default y if GPIO
 

cmake/compiler/gcc/target_riscv.cmake

@@ -13,10 +13,10 @@ else()
     string(CONCAT riscv_march ${riscv_march} "32i")
 endif()
 
-if (CONFIG_RISCV_MUL_ISA)
+if (CONFIG_RISCV_ISA_EXT_M)
     string(CONCAT riscv_march ${riscv_march} "m")
 endif()
-if (CONFIG_RISCV_ATOMICS_ISA)
+if (CONFIG_RISCV_ISA_EXT_A)
     string(CONCAT riscv_march ${riscv_march} "a")
 endif()
 
@@ -34,7 +34,7 @@ if(CONFIG_FPU)
     endif()
 endif()
 
-if(CONFIG_COMPRESSED_ISA)
+if(CONFIG_RISCV_ISA_EXT_C)
     string(CONCAT riscv_march ${riscv_march} "c")
 endif()
 

soc/riscv/esp32c3/Kconfig.soc

@@ -11,6 +11,9 @@ config SOC_ESP32C3
 	select PINCTRL
 	select XIP
 	select HAS_ESPRESSIF_HAL
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 
 if SOC_ESP32C3
 

soc/riscv/litex-vexriscv/Kconfig.soc

@@ -6,6 +6,9 @@ config SOC_RISCV32_LITEX_VEXRISCV
 	select RISCV
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 
 if SOC_RISCV32_LITEX_VEXRISCV
 

soc/riscv/openisa_rv32m1/Kconfig.soc

@@ -18,6 +18,9 @@ config SOC_OPENISA_RV32M1_RISCV32
 	select HAS_RV32M1_FTFX
 	select HAS_FLASH_LOAD_OFFSET
 	select BUILD_OUTPUT_HEX
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 	help
 	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
 	  this option to target the RI5CY or ZERO-RISCY core. This

soc/riscv/riscv-ite/it8xxx2/Kconfig.series

@@ -4,10 +4,7 @@
 config SOC_SERIES_RISCV32_IT8XXX2
 	bool "ITE IT8XXX2 implementation"
 	#depends on RISCV
-	select COMPRESSED_ISA
 	select CPU_HAS_FPU
-	select RISCV_ATOMICS_ISA
-	select RISCV_MUL_ISA
 	select SOC_FAMILY_RISCV_ITE
 	help
 	    Enable support for ITE IT8XXX2

soc/riscv/riscv-ite/it8xxx2/Kconfig.soc

@@ -9,6 +9,10 @@ config SOC_IT8XXX2
 	bool "ITE IT8XXX2 system implementation"
 	select RISCV
 	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice
 

soc/riscv/riscv-privilege/andes_v5/Kconfig.soc

@@ -9,6 +9,8 @@ config SOC_RISCV_ANDES_AE350
 	bool "Andes AE350 SoC implementation"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 
 endchoice
 
@@ -20,9 +22,11 @@ default RV32I_CPU
 
 config RV32I_CPU
 	bool "RISCV32 CPU ISA"
+	select RISCV_ISA_RV32I
 
 config RV64I_CPU
 	bool "RISCV64 CPU ISA"
+	select RISCV_ISA_RV64I
 	select 64BIT
 
 endchoice

soc/riscv/riscv-privilege/gd32vf103/Kconfig.series

@@ -8,7 +8,6 @@ config SOC_SERIES_GD32VF103
 	select RISCV
 	select SOC_FAMILY_RISCV_PRIVILEGE
 	select ATOMIC_OPERATIONS_C
-	select COMPRESSED_ISA
 	select INCLUDE_RESET_VECTOR
 	select BUILD_OUTPUT_HEX
 	select XIP

soc/riscv/riscv-privilege/gd32vf103/Kconfig.soc

@@ -9,5 +9,9 @@ choice
 
 config SOC_GD32VF103
 	bool "GD32VF103"
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice

soc/riscv/riscv-privilege/miv/Kconfig.soc

@@ -11,5 +11,8 @@ config SOC_RISCV32_MIV
 	bool "Microsemi Mi-V system implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 
 endchoice

soc/riscv/riscv-privilege/mpfs/Kconfig.soc

@@ -15,6 +15,10 @@ config SOC_MPFS
 	select USE_SWITCH
 	select CPU_HAS_FPU
 	select SCHED_IPI_SUPPORTED
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice
 

soc/riscv/riscv-privilege/neorv32/Kconfig.series

@@ -4,6 +4,9 @@
 config SOC_SERIES_NEORV32
 	bool "NEORV32 Processor"
 	select RISCV
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 	select SOC_FAMILY_RISCV_PRIVILEGE
 	help
 	  Enable support for the NEORV32 Processor (SoC).

soc/riscv/riscv-privilege/neorv32/Kconfig.soc

@@ -24,7 +24,7 @@ config SOC_NEORV32_VERSION
 
 config SOC_NEORV32_ISA_C
 	bool "RISC-V ISA Extension \"C\""
-	select COMPRESSED_ISA
+	select RISCV_ISA_EXT_C
 	help
 	  Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
 	  "C" extension (Compressed Instructions).

soc/riscv/riscv-privilege/sifive-freedom/Kconfig.soc

@@ -11,17 +11,28 @@ config SOC_RISCV_SIFIVE_FREEDOM
 	bool "SiFive Freedom SOC implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
 
 config SOC_RISCV_SIFIVE_FU540
 	bool "SiFive Freedom U540 SOC implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select 64BIT
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 config SOC_RISCV_SIFIVE_FU740
 	bool "SiFive Freedom U740 SOC implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select 64BIT
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.soc

@@ -9,5 +9,9 @@ config SOC_JH7100
 	bool "Starfive JH7100"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice

soc/riscv/riscv-privilege/telink_b91/Kconfig.series

@@ -4,6 +4,10 @@
 config SOC_SERIES_RISCV_TELINK_B91
 	bool "Telink B91 SoC Implementation"
 	select RISCV
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 	select SOC_FAMILY_RISCV_PRIVILEGE
 	select HAS_TELINK_DRIVERS
 	help

soc/riscv/riscv-privilege/telink_b91/Kconfig.soc

@@ -7,6 +7,10 @@ depends on SOC_SERIES_RISCV_TELINK_B91
 
 config B91_CPU_RISCV32
 	bool "RISCV32 CPU Architecture"
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice
 

soc/riscv/riscv-privilege/virt/Kconfig.soc

@@ -9,5 +9,8 @@ config SOC_RISCV_VIRT
 	bool "QEMU RISC-V VirtIO Board"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 
 endchoice