ext/hal/nxp/imx: Import the nxp imx6 freertos bsp
This code component is used to add Zephyr support on iMX6SX
processors, exclusively on Cortex M4 core, and to speed up the
development process it was decided to have it based on NXP FreeRTOS BSP
implementation.
The i.MX FreeRTOS BSP is split into separate downloadable packages,
based on SoC. The packages share most of the peripheral driver files
and here they are combined together.
The source code was imported from the following folders:
FreeRTOS_BSP_1.0.1_iMX6SX/platform/drivers
FreeRTOS_BSP_1.0.1_iMX6SX/platform/devices
This source code depends on headers and sources from zephyr:
ext/hal/cmsis
Origin: i.MX 6SoloX FreeRTOS BSP 1.0.1 for Cortex-M4 Peripheral Driver
License: BSD 3-Clause
URL: https://www.nxp.com/webapp/Download?colCode=FreeRTOS_MX6SX_1.0.1_LINUX&appType=license
commit: no commit hash
Purpose: The peripheral driver wraps the H/W for i.MX6SX M4 core
Maintained-by: External
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This commit is contained in:
Stanislav Poboril
Maureen Helm
parent
5e7e1cba69
commit
1112f25274
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@ -1,25 +1,34 @@
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iMX7D Port
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iMX7D and MX6SX Port
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#####################
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Origin:
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iMX7D NXP FreeRTOS BSP Peripheral Driver
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i.MX 7Dual/Solo FreeRTOS BSP for Cortex-M4 Peripheral Driver
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https://www.nxp.com/webapp/Download?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=license
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i.MX 6SoloX FreeRTOS BSP 1.0.1 for Cortex-M4 Peripheral Driver
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https://www.nxp.com/webapp/Download?colCode=FreeRTOS_MX6SX_1.0.1_LINUX&appType=license
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Status:
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FreeRTOS_iMX7D_1.0.1
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FreeRTOS_MX6SX_1.0.1
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Purpose:
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The peripheral driver wrap the H/W
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Description:
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This code component is used to add Zephyr support on iMX7 processors,
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exclusively on Cortex M4 core, and to speed up the development process
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it was decided to have it based on NXP FreeRTOS BSP implementation.
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This code component is used to add Zephyr support on iMX7 and iMX6SX
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processors, exclusively on Cortex M4 core, and to speed up the development
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process it was decided to have it based on NXP FreeRTOS BSP implementation.
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||||
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The i.MX FreeRTOS BSP is split into separate downloadable packages,
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based on SoC. The packages share most of the peripheral driver files
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and here they are combined together.
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The source code was imported from the following folders:
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FreeRTOS_BSP_1.0.1_iMX7D/platform/drivers
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FreeRTOS_BSP_1.0.1_iMX6SX/platform/drivers
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FreeRTOS_BSP_1.0.1_iMX7D/platform/devices
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FreeRTOS_BSP_1.0.1_iMX6SX/platform/devices
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Dependencies:
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This source code depends on headers and sources from zephyr:
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@ -27,6 +36,7 @@ Dependencies:
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URL:
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https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab
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https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX?tab=Design_Tools_Tab
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commit:
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No commit hash
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@ -39,3 +49,4 @@ License:
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License Link:
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https://www.nxp.com/webapp/sps/download/license.jsp?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=file1&DOWNLOAD_ID=null
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https://www.nxp.com/webapp/sps/download/license.jsp?colCode=FreeRTOS_MX6SX_1.0.1_LINUX&appType=file1&DOWNLOAD_ID=null
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2
ext/hal/nxp/imx/devices/MCIMX6X/CMakeLists.txt
Normal file
2
ext/hal/nxp/imx/devices/MCIMX6X/CMakeLists.txt
Normal file
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@ -0,0 +1,2 @@
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zephyr_include_directories(.)
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zephyr_sources(clock_freq.c)
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41139
ext/hal/nxp/imx/devices/MCIMX6X/MCIMX6X_M4.h
Normal file
41139
ext/hal/nxp/imx/devices/MCIMX6X/MCIMX6X_M4.h
Normal file
File diff suppressed because it is too large
Load diff
265
ext/hal/nxp/imx/devices/MCIMX6X/clock_freq.c
Executable file
265
ext/hal/nxp/imx/devices/MCIMX6X/clock_freq.c
Executable file
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
|
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* are permitted provided that the following conditions are met:
|
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*
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||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
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* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "clock_freq.h"
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#include "ccm_imx6sx.h"
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#include "ccm_analog_imx6sx.h"
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/*FUNCTION**********************************************************************
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*
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* Function Name : get_epit_clock_freq
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* Description : Get clock frequency applys to the EPIIT module
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*
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*END**************************************************************************/
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uint32_t get_epit_clock_freq(EPIT_Type* base)
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{
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uint32_t root;
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uint32_t hz;
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uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf;
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/* Different instance has the same clock root, it's different from i.mx7d. */
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/* Get the clock root according to the mux node of clock tree. */
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if(CCM_GetRootMux(CCM, ccmRootPerclkClkSel) == ccmRootmuxPerclkClkOsc24m)
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{
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root = ccmRootmuxPerclkClkOsc24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = 0;
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divAhbPodf = 0;
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divPeriphClk2Podf = 0;
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}
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else if(CCM_GetRootMux(CCM, ccmRootPeriphClkSel) == ccmRootmuxPeriphClkPrePeriphClkSel)
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{
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root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel);
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/* Here do not show all the clock root source,
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if user use other clock root source, such as PLL2_PFD2, please
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add it as follows according to the clock tree of CCM in reference manual. */
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switch(root)
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{
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case ccmRootmuxPrePeriphClkPll2:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = 0;
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break;
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default:
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return 0;
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}
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}
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else if(CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) == ccmRootmuxPeriphClk2OSC24m)
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{
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root = ccmRootmuxPeriphClk2OSC24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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}
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else
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{
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root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
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/* Here do not show all the clock root source,
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if user use other clock root source, such as PLL3_BYP, please
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add it as follows according to the clock tree of CCM in reference manual. */
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switch(root)
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{
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case ccmRootmuxPll3SwClkPll3:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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break;
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default:
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return 0;
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}
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}
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return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) / (divAhbPodf + 1) / (divPeriphClk2Podf + 1);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : get_I2C_clock_freq
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* Description : Get clock frequency applys to the I2C module
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*
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*END**************************************************************************/
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uint32_t get_i2c_clock_freq(I2C_Type* base)
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{
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uint32_t root;
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uint32_t hz;
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uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf;
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/* Different instance has the same clock root, it's different from i.mx7d. */
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/* Get the clock root according to the mux node of clock tree. */
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if(CCM_GetRootMux(CCM, ccmRootPerclkClkSel) == ccmRootmuxPerclkClkOsc24m)
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{
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root = ccmRootmuxPerclkClkOsc24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = 0;
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divAhbPodf = 0;
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divPeriphClk2Podf = 0;
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}
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else if(CCM_GetRootMux(CCM, ccmRootPeriphClkSel) == ccmRootmuxPeriphClkPrePeriphClkSel)
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{
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root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel);
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/* Here do not show all the clock root source,
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if user use other clock root source, such as PLL2_PFD2, please
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add it as follows according to the clock tree of CCM in reference manual. */
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switch(root)
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{
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case ccmRootmuxPrePeriphClkPll2:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = 0;
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break;
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default:
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return 0;
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}
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}
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else if(CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) == ccmRootmuxPeriphClk2OSC24m)
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{
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root = ccmRootmuxPeriphClk2OSC24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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}
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else
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{
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root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
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/* Here do not show all the clock root source,
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if user use other clock root source, such as PLL3_BYP, please
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add it as follows according to the clock tree of CCM in reference manual. */
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switch(root)
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{
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case ccmRootmuxPll3SwClkPll3:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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break;
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default:
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return 0;
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}
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}
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return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) / (divAhbPodf + 1) / (divPeriphClk2Podf + 1);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : get_ecspi_clock_freq
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* Description : Get clock frequency applys to the ECSPI module
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*
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*END**************************************************************************/
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uint32_t get_ecspi_clock_freq(ECSPI_Type* base)
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{
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uint32_t root;
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uint32_t hz;
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uint32_t divEcspiClkPodf, divStatic;
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if(CCM_GetRootMux(CCM, ccmRootEcspiClkSel) == ccmRootmuxEcspiClkOsc24m)
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{
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root = ccmRootmuxEcspiClkOsc24m;
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hz = 24000000;
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divEcspiClkPodf = CCM_GetRootDivider(CCM, ccmRootEcspiClkPodf);
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divStatic = 0;
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}
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else
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{
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root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
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/* Here do not show all the clock root source,
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if user use other clock root source, such as PLL3_BYP, please
|
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add it as follows according to the clock tree of CCM in reference manual. */
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switch(root)
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{
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case ccmRootmuxPll3SwClkPll3:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
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divEcspiClkPodf = CCM_GetRootDivider(CCM, ccmRootEcspiClkPodf);
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divStatic = 7;
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break;
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default:
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return 0;
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}
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}
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return hz / (divEcspiClkPodf + 1) / (divStatic + 1);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : get_uart_clock_freq
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* Description : Get clock frequency applys to the UART module
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*
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*END**************************************************************************/
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uint32_t get_uart_clock_freq(UART_Type* base)
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{
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uint32_t root;
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uint32_t hz;
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uint32_t divUartClkPodf, divStatic;
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if(CCM_GetRootMux(CCM, ccmRootUartClkSel) == ccmRootmuxUartClkOsc24m)
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{
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root = ccmRootmuxUartClkOsc24m;
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hz = 24000000;
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divUartClkPodf = CCM_GetRootDivider(CCM, ccmRootUartClkPodf);
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divStatic = 0;
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}
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else
|
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{
|
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root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
|
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/* Here do not show all the clock root source,
|
||||
if user use other clock root source, such as PLL3_BYP, please
|
||||
add it as follows according to the clock tree of CCM in reference manual. */
|
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switch(root)
|
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{
|
||||
case ccmRootmuxPll3SwClkPll3:
|
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
|
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divUartClkPodf = CCM_GetRootDivider(CCM, ccmRootUartClkPodf);
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divStatic = 5;
|
||||
break;
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default:
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return 0;
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}
|
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}
|
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|
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return hz / (divUartClkPodf + 1) / (divStatic + 1);
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}
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|
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/*******************************************************************************
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* EOF
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******************************************************************************/
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90
ext/hal/nxp/imx/devices/MCIMX6X/clock_freq.h
Executable file
90
ext/hal/nxp/imx/devices/MCIMX6X/clock_freq.h
Executable file
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CLOCK_FREQ_H__
|
||||
#define __CLOCK_FREQ_H__
|
||||
|
||||
#include "device_imx.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup clock_freq_helper
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Get clock frequency applys to the EPIT module
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return clock frequency (in HZ) applys to the EPIT module
|
||||
*/
|
||||
uint32_t get_epit_clock_freq(EPIT_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Get clock frequency applys to the I2C module
|
||||
*
|
||||
* @param base I2C base pointer.
|
||||
* @return clock frequency (in HZ) applys to the I2C module
|
||||
*/
|
||||
uint32_t get_i2c_clock_freq(I2C_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Get clock frequency applys to the ECSPI module
|
||||
*
|
||||
* @param base ECSPI base pointer.
|
||||
* @return clock frequency (in HZ) applys to the ECSPI module
|
||||
*/
|
||||
uint32_t get_ecspi_clock_freq(ECSPI_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Get clock frequency applys to the UART module
|
||||
*
|
||||
* @param base UART base pointer.
|
||||
* @return clock frequency (in HZ) applys to the UART module
|
||||
*/
|
||||
uint32_t get_uart_clock_freq(UART_Type* base);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __CLOCK_FREQ_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
74
ext/hal/nxp/imx/devices/MCIMX6X/device_imx.h
Normal file
74
ext/hal/nxp/imx/devices/MCIMX6X/device_imx.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
** Abstract:
|
||||
** Common include file for CMSIS register access layer headers.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#ifndef __DEVICE_IMX_H__
|
||||
#define __DEVICE_IMX_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_MCIMX6X_M4)
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MCIMX6X_M4.h"
|
||||
#define RDC_SEMAPHORE_MASTER_SELF (5)
|
||||
#define SEMA4_PROCESSOR_SELF (1)
|
||||
|
||||
#elif defined(CONFIG_SOC_MCIMX7D_M4)
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MCIMX7D_M4.h"
|
||||
|
||||
#define RDC_SEMAPHORE_MASTER_SELF (6)
|
||||
#define SEMA4_PROCESSOR_SELF (1)
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __DEVICE_IMX_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
519
ext/hal/nxp/imx/drivers/adc_imx6sx.c
Executable file
519
ext/hal/nxp/imx/drivers/adc_imx6sx.c
Executable file
|
|
@ -0,0 +1,519 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "adc_imx6sx.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_Init
|
||||
* Description : Initialize ADC to reset state and initialize with initialize
|
||||
* structure.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig)
|
||||
{
|
||||
assert(initConfig);
|
||||
|
||||
/* Reset ADC register to its default value. */
|
||||
ADC_Deinit(base);
|
||||
|
||||
/* Set hardware average function and number. */
|
||||
if (initConfig->averageNumber != adcAvgNumNone)
|
||||
{
|
||||
ADC_GC_REG(base) |= ADC_GC_AVGE_MASK;
|
||||
ADC_CFG_REG(base) |= ADC_CFG_AVGS(initConfig->averageNumber);
|
||||
}
|
||||
|
||||
/* Set resolution mode. */
|
||||
ADC_CFG_REG(base) |= ADC_CFG_MODE(initConfig->resolutionMode);
|
||||
|
||||
/* Set clock source. */
|
||||
ADC_SetClockSource(base, initConfig->clockSource, initConfig->divideRatio);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_Deinit
|
||||
* Description : This function reset ADC module register content to its
|
||||
* default value.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_Deinit(ADC_Type* base)
|
||||
{
|
||||
/* Reset ADC Module Register content to default value */
|
||||
ADC_HC0_REG(base) = ADC_HC0_ADCH_MASK;
|
||||
ADC_HC1_REG(base) = ADC_HC1_ADCH_MASK;
|
||||
ADC_R0_REG(base) = 0x0;
|
||||
ADC_R1_REG(base) = 0x0;
|
||||
ADC_CFG_REG(base) = ADC_CFG_ADSTS(2);
|
||||
ADC_GC_REG(base) = 0x0;
|
||||
ADC_GS_REG(base) = ADC_GS_CALF_MASK | ADC_GS_AWKST_MASK;
|
||||
ADC_CV_REG(base) = 0x0;
|
||||
ADC_OFS_REG(base) = 0x0;
|
||||
ADC_CAL_REG(base) = 0x0;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetConvertResultOverwrite
|
||||
* Description : Enable or disable ADC overwrite conversion result register.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable)
|
||||
{
|
||||
if(enable)
|
||||
ADC_CFG_REG(base) |= ADC_CFG_OVWREN_MASK;
|
||||
else
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_OVWREN_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetConvertTrigMode
|
||||
* Description : This function is used to set conversion trigger mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode)
|
||||
{
|
||||
assert(mode <= adcHardwareTrigger);
|
||||
|
||||
if(mode == adcHardwareTrigger)
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADTRG_MASK;
|
||||
else
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADTRG_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetConvertSpeed
|
||||
* Description : This function is used to set conversion speed mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode)
|
||||
{
|
||||
assert(mode <= adcHighSpeed);
|
||||
|
||||
if(mode == adcHighSpeed)
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADHSC_MASK;
|
||||
else
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADHSC_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetSampleTimeDuration
|
||||
* Description : This function is used to set sample time duration.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration)
|
||||
{
|
||||
assert(duration <= adcSamplePeriodClock24);
|
||||
|
||||
switch(duration)
|
||||
{
|
||||
case adcSamplePeriodClock2:
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(0U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock4:
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(1U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock6:
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(2U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock8:
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(3U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock12:
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(0U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock16:
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(1U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock20:
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(2U);
|
||||
break;
|
||||
|
||||
case adcSamplePeriodClock24:
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK;
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) |
|
||||
ADC_CFG_ADSTS(3U);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetPowerMode
|
||||
* Description : This function is used to set power mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode)
|
||||
{
|
||||
assert(powerMode <= adcLowPowerMode);
|
||||
|
||||
if(powerMode == adcLowPowerMode)
|
||||
ADC_CFG_REG(base) |= ADC_CFG_ADLPC_MASK;
|
||||
else
|
||||
ADC_CFG_REG(base) &= ~ADC_CFG_ADLPC_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetClockSource
|
||||
* Description : This function is used to set ADC clock source.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div)
|
||||
{
|
||||
assert(source <= adcAsynClock);
|
||||
assert(div <= adcInputClockDiv8);
|
||||
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADIV_MASK)) |
|
||||
ADC_CFG_ADIV(div);
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADICLK_MASK)) |
|
||||
ADC_CFG_ADICLK(source);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetAsynClockOutput
|
||||
* Description : This function is used to enable asynchronous clock source output
|
||||
* regardless of the state of ADC.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetAsynClockOutput(ADC_Type* base, bool enable)
|
||||
{
|
||||
if(enable)
|
||||
ADC_GC_REG(base) |= ADC_GC_ADACKEN_MASK;
|
||||
else
|
||||
ADC_GC_REG(base) &= ~ADC_GC_ADACKEN_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetCalibration
|
||||
* Description : Enable or disable calibration function.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetCalibration(ADC_Type* base, bool enable)
|
||||
{
|
||||
if(enable)
|
||||
ADC_GC_REG(base) |= ADC_GC_CAL_MASK;
|
||||
else
|
||||
ADC_GC_REG(base) &= ~ADC_GC_CAL_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetConvertCmd
|
||||
* Description : Enable continuous conversion and start a conversion on target channel.
|
||||
* This function is only used for software trigger mode. If configured as
|
||||
* hardware trigger mode, this function just enable continuous conversion
|
||||
* and not start the conversion.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
/* Enable continuous conversion. */
|
||||
if(enable)
|
||||
{
|
||||
ADC_GC_REG(base) |= ADC_GC_ADCO_MASK;
|
||||
/* Start the conversion. */
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) |
|
||||
ADC_HC0_ADCH(channel);
|
||||
else /* Just set the channel. */
|
||||
ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) |
|
||||
ADC_HC1_ADCH(channel);
|
||||
}
|
||||
else
|
||||
ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_TriggerSingleConvert
|
||||
* Description : Enable single conversion and trigger single time conversion
|
||||
* on target imput channel. If configured as hardware trigger
|
||||
* mode, this function just set input channel and not start a
|
||||
* conversion.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
/* Enable single conversion. */
|
||||
ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK;
|
||||
/* Start the conversion. */
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) |
|
||||
ADC_HC0_ADCH(channel);
|
||||
else /* Just set the channel. */
|
||||
ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) |
|
||||
ADC_HC1_ADCH(channel);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetAverageNum
|
||||
* Description : This function is used to enable hardware aaverage function
|
||||
* and set hardware average number. If avgNum is equal to
|
||||
* adcAvgNumNone, it means disable hardware average function.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum)
|
||||
{
|
||||
assert(avgNum <= adcAvgNumNone);
|
||||
|
||||
if(avgNum != adcAvgNumNone)
|
||||
{
|
||||
/* Enable hardware average function. */
|
||||
ADC_GC_REG(base) |= ADC_GC_AVGE_MASK;
|
||||
/* Set hardware average number. */
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_AVGS_MASK)) |
|
||||
ADC_CFG_AVGS(avgNum);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable hardware average function. */
|
||||
ADC_GC_REG(base) &= ~ADC_GC_AVGE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_StopConvert
|
||||
* Description : This function is used to stop all conversions.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_StopConvert(ADC_Type* base)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
/* According trigger mode to set specific register. */
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
ADC_HC0_REG(base) |= ADC_HC0_ADCH_MASK;
|
||||
else
|
||||
ADC_HC1_REG(base) |= ADC_HC1_ADCH_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_GetConvertResult
|
||||
* Description : This function is used to get conversion result.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint16_t ADC_GetConvertResult(ADC_Type* base)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
return (uint16_t)((ADC_R0_REG(base) & ADC_R0_D_MASK) >> ADC_R0_D_SHIFT);
|
||||
else
|
||||
return (uint16_t)((ADC_R1_REG(base) & ADC_R1_D_MASK) >> ADC_R1_D_SHIFT);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetCmpMode
|
||||
* Description : This function is used to enable compare function
|
||||
* and set comparer mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2)
|
||||
{
|
||||
assert(cmpMode <= adcCmpModeDisable);
|
||||
|
||||
switch(cmpMode)
|
||||
{
|
||||
case adcCmpModeLessThanCmpVal1:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) &= ~(ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
break;
|
||||
|
||||
case adcCmpModeGreaterThanCmpVal1:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACFGT_MASK) & (~ADC_GC_ACREN_MASK);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
break;
|
||||
|
||||
case adcCmpModeOutRangNotInclusive:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK);
|
||||
if(cmpVal1 <= cmpVal2)
|
||||
{
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2);
|
||||
}
|
||||
break;
|
||||
|
||||
case adcCmpModeInRangNotInclusive:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK);
|
||||
if(cmpVal1 > cmpVal2)
|
||||
{
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2);
|
||||
}
|
||||
break;
|
||||
|
||||
case adcCmpModeInRangInclusive:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK;
|
||||
if(cmpVal1 <= cmpVal2)
|
||||
{
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2);
|
||||
}
|
||||
break;
|
||||
|
||||
case adcCmpModeOutRangInclusive:
|
||||
ADC_GC_REG(base) |= ADC_GC_ACFE_MASK;
|
||||
ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK;
|
||||
if(cmpVal1 > cmpVal2)
|
||||
{
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1);
|
||||
ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2);
|
||||
}
|
||||
break;
|
||||
|
||||
case adcCmpModeDisable:
|
||||
ADC_GC_REG(base) &= ~ADC_GC_ACFE_MASK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetCorrectionMode
|
||||
* Description : This function is used to set offset correct mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode)
|
||||
{
|
||||
if(correctMode)
|
||||
ADC_OFS_REG(base) |= ADC_OFS_SIGN_MASK;
|
||||
else
|
||||
ADC_OFS_REG(base) &= ~ADC_OFS_SIGN_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetIntCmd
|
||||
* Description : Enables or disables ADC conversion complete interrupt request.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetIntCmd(ADC_Type* base, bool enable)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
{
|
||||
if(enable)
|
||||
ADC_HC0_REG(base) |= ADC_HC0_AIEN_MASK;
|
||||
else
|
||||
ADC_HC0_REG(base) &= ~ADC_HC0_AIEN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(enable)
|
||||
ADC_HC1_REG(base) |= ADC_HC1_AIEN_MASK;
|
||||
else
|
||||
ADC_HC1_REG(base) &= ~ADC_HC1_AIEN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_IsConvertComplete
|
||||
* Description : This function is used to get ADC conversion complete status.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
bool ADC_IsConvertComplete(ADC_Type* base)
|
||||
{
|
||||
uint8_t triggerMode;
|
||||
|
||||
triggerMode = ADC_GetConvertTrigMode(base);
|
||||
if(triggerMode == adcSoftwareTrigger)
|
||||
return (bool)((ADC_HS_REG(base) & ADC_HS_COCO0_MASK) >> ADC_HS_COCO0_SHIFT);
|
||||
else
|
||||
return (bool)((ADC_HS_REG(base) & ADC_HS_COCO1_MASK) >> ADC_HS_COCO1_SHIFT);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : ADC_SetDmaCmd
|
||||
* Description : Enable or disable DMA request.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void ADC_SetDmaCmd(ADC_Type* base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
ADC_GC_REG(base) |= ADC_GC_DMAEN_MASK;
|
||||
else
|
||||
ADC_GC_REG(base) &= ~ADC_GC_DMAEN_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
513
ext/hal/nxp/imx/drivers/adc_imx6sx.h
Executable file
513
ext/hal/nxp/imx/drivers/adc_imx6sx.h
Executable file
|
|
@ -0,0 +1,513 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_IMX6SX_H__
|
||||
#define __ADC_IMX6SX_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "device_imx.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup adc_imx6sx_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief ADC module initialize structure. */
|
||||
typedef struct _adc_init_config
|
||||
{
|
||||
uint8_t clockSource; /*!< Select input clock source to generate the internal conversion clock.*/
|
||||
uint8_t divideRatio; /*!< Selects divide ratio used to generate the internal conversion clock.*/
|
||||
uint8_t averageNumber; /*!< The average number for hardware average function.*/
|
||||
uint8_t resolutionMode; /*!< Set ADC resolution mode.*/
|
||||
} adc_init_config_t;
|
||||
|
||||
/*! @brief ADC hardware average number. */
|
||||
enum _adc_average_number
|
||||
{
|
||||
adcAvgNum4 = 0U, /*!< ADC Hardware Average Number is set to 4.*/
|
||||
adcAvgNum8 = 1U, /*!< ADC Hardware Average Number is set to 8.*/
|
||||
adcAvgNum16 = 2U, /*!< ADC Hardware Average Number is set to 16.*/
|
||||
adcAvgNum32 = 3U, /*!< ADC Hardware Average Number is set to 32.*/
|
||||
adcAvgNumNone = 4U, /*!< Disable ADC Hardware Average.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC conversion trigger select. */
|
||||
enum _adc_convert_trigger_mode
|
||||
{
|
||||
adcSoftwareTrigger = 0U, /*!< ADC software trigger a conversion.*/
|
||||
adcHardwareTrigger = 1U, /*!< ADC hardware trigger a conversion.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC conversion speed configure. */
|
||||
enum _adc_convert_speed_config
|
||||
{
|
||||
adcNormalSpeed = 0U, /*!< ADC set as normal conversion speed.*/
|
||||
adcHighSpeed = 1U, /*!< ADC set as high conversion speed.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC sample time duration. */
|
||||
enum _adc_sample_time_duration
|
||||
{
|
||||
adcSamplePeriodClock2, /*!< The sample time duration is set as 2 ADC clocks.*/
|
||||
adcSamplePeriodClock4, /*!< The sample time duration is set as 4 ADC clocks.*/
|
||||
adcSamplePeriodClock6, /*!< The sample time duration is set as 6 ADC clocks.*/
|
||||
adcSamplePeriodClock8, /*!< The sample time duration is set as 8 ADC clocks.*/
|
||||
adcSamplePeriodClock12, /*!< The sample time duration is set as 12 ADC clocks.*/
|
||||
adcSamplePeriodClock16, /*!< The sample time duration is set as 16 ADC clocks.*/
|
||||
adcSamplePeriodClock20, /*!< The sample time duration is set as 20 ADC clocks.*/
|
||||
adcSamplePeriodClock24, /*!< The sample time duration is set as 24 ADC clocks.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC low power configure. */
|
||||
enum _adc_power_mode
|
||||
{
|
||||
adcNormalPowerMode = 0U, /*!< ADC hard block set as normal power mode.*/
|
||||
adcLowPowerMode = 1U, /*!< ADC hard block set as low power mode.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC conversion resolution mode. */
|
||||
enum _adc_resolution_mode
|
||||
{
|
||||
adcResolutionBit8 = 0U, /*!< ADC resolution set as 8 bit conversion mode.*/
|
||||
adcResolutionBit10 = 1U, /*!< ADC resolution set as 10 bit conversion mode.*/
|
||||
adcResolutionBit12 = 2U, /*!< ADC resolution set as 12 bit conversion mode.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC input clock divide. */
|
||||
enum _adc_clock_divide
|
||||
{
|
||||
adcInputClockDiv1 = 0U, /*!< Input clock divide 1 to generate internal clock.*/
|
||||
adcInputClockDiv2 = 1U, /*!< Input clock divide 2 to generate internal clock.*/
|
||||
adcInputClockDiv4 = 2U, /*!< Input clock divide 4 to generate internal clock.*/
|
||||
adcInputClockDiv8 = 3U, /*!< Input clock divide 8 to generate internal clock.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC clock source. */
|
||||
enum _adc_clock_source
|
||||
{
|
||||
adcIpgClock = 0U, /*!< Select ipg clock as input clock source.*/
|
||||
adcIpgClockDivide2 = 1U, /*!< Select ipg clock divide 2 as input clock source.*/
|
||||
adcAsynClock = 3U, /*!< Select asynchronous clock as input clock source.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC comparer work mode configuration. */
|
||||
enum _adc_compare_mode
|
||||
{
|
||||
adcCmpModeLessThanCmpVal1, /*!< Compare true if the result is less than compare value 1.*/
|
||||
adcCmpModeGreaterThanCmpVal1, /*!< Compare true if the result is greater than or equal to compare value 1.*/
|
||||
adcCmpModeOutRangNotInclusive, /*!< Compare true if the result is less than compare value 1 or the result is Greater than compare value 2.*/
|
||||
adcCmpModeInRangNotInclusive, /*!< Compare true if the result is less than compare value 1 and the result is greater than compare value 2.*/
|
||||
adcCmpModeInRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 and the result is less than or equal to compare value 2.*/
|
||||
adcCmpModeOutRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 or the result is less than or equal to compare value 2.*/
|
||||
adcCmpModeDisable, /*!< ADC compare function disable.*/
|
||||
};
|
||||
|
||||
/*! @brief ADC general status flag. */
|
||||
enum _adc_general_status_flag
|
||||
{
|
||||
adcFlagAsynWakeUpInt = 1U << 0, /*!< Indicate asynchronous wake up interrupt occurred in stop mode.*/
|
||||
adcFlagCalibrateFailed = 1U << 1, /*!< Indicate the result of the calibration sequence.*/
|
||||
adcFlagConvertActive = 1U << 2, /*!< Indicate a conversion is in the process.*/
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name ADC Module Initialization and Configuration Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize ADC to reset state and initialize with initialize structure.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param initConfig ADC initialize structure.
|
||||
*/
|
||||
void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig);
|
||||
|
||||
/*!
|
||||
* @brief This function reset ADC module register content to its default value.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
*/
|
||||
void ADC_Deinit(ADC_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Enable or disable ADC module overwrite conversion result.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param enable Enable/Disable conversion result overwire function.
|
||||
* - true: Enable conversion result overwire.
|
||||
* - false: Disable conversion result overwrite.
|
||||
*/
|
||||
void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief This function set ADC module conversion trigger mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param mode Conversion trigger (see @ref _adc_convert_trigger_mode enumeration).
|
||||
*/
|
||||
void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode);
|
||||
|
||||
/*!
|
||||
* @brief This function is used to get conversion trigger mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Conversion trigger mode (see @ref _adc_convert_trigger_mode enumeration).
|
||||
*/
|
||||
static inline uint8_t ADC_GetConvertTrigMode(ADC_Type* base)
|
||||
{
|
||||
return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADTRG_MASK) >> ADC_CFG_ADTRG_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief This function set ADC module conversion speed mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param mode Conversion speed mode (see @ref _adc_convert_speed_config enumeration).
|
||||
*/
|
||||
void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode);
|
||||
|
||||
/*!
|
||||
* @brief This function get ADC module conversion speed mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Conversion speed mode.
|
||||
*/
|
||||
static inline uint8_t ADC_GetConvertSpeed(ADC_Type* base)
|
||||
{
|
||||
return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADHSC_MASK) >> ADC_CFG_ADHSC_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief This function set ADC module sample time duration.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param duration Sample time duration (see @ref _adc_sample_time_duration enumeration).
|
||||
*/
|
||||
void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration);
|
||||
|
||||
/*!
|
||||
* @brief This function set ADC module power mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param powerMode power mode (see @ref _adc_power_mode enumeration).
|
||||
*/
|
||||
void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode);
|
||||
|
||||
/*!
|
||||
* @brief This function get ADC module power mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Power mode.
|
||||
*/
|
||||
static inline uint8_t ADC_GetPowerMode(ADC_Type* base)
|
||||
{
|
||||
return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADLPC_MASK) >> ADC_CFG_ADLPC_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief This function set ADC module clock source.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param source Conversion clock source (see @ref _adc_clock_source enumeration).
|
||||
* @param div Input clock divide ratio (see @ref _adc_clock_divide enumeration).
|
||||
*/
|
||||
void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div);
|
||||
|
||||
/*!
|
||||
* @brief This function enable asynchronous clock source output regardless of the
|
||||
* state of ADC and input clock select of ADC module. Setting this bit
|
||||
* allows the clock to be used even while the ADC is idle or operating from
|
||||
* a different clock source.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param enable Asynchronous clock output enable.
|
||||
* - true: Enable asynchronous clock output regardless of the state of ADC;
|
||||
* - false: Only enable if selected as ADC input clock source and a
|
||||
* ADC conversion is active.
|
||||
*/
|
||||
void ADC_SetAsynClockOutput(ADC_Type* base, bool enable);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name ADC Calibration Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief This function is used to enable or disable calibration function.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param enable Enable/Disable calibration function.
|
||||
* - true: Enable calibration function.
|
||||
* - false: Disable calibration function.
|
||||
*/
|
||||
void ADC_SetCalibration(ADC_Type* base, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief This function is used to get calibrate result value.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Calibration result value.
|
||||
*/
|
||||
static inline uint8_t ADC_GetCalibrationResult(ADC_Type* base)
|
||||
{
|
||||
return (uint8_t)((ADC_CAL_REG(base) & ADC_CAL_CAL_CODE_MASK) >> ADC_CAL_CAL_CODE_SHIFT);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name ADC Module Conversion Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable continuous conversion and start a conversion on target channel.
|
||||
* This function is only used for software trigger mode. If configured as
|
||||
* hardware trigger mode, this function just enable continuous conversion mode
|
||||
* and not start the conversion.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param channel Input channel selection.
|
||||
* @param enable Enable/Disable continuous conversion.
|
||||
* - true: Enable and start continuous conversion.
|
||||
* - false: Disable continuous conversion.
|
||||
*/
|
||||
void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Enable single conversion and trigger single time conversion
|
||||
* on target input channel.If configured as hardware trigger
|
||||
* mode, this function just set input channel and not start a
|
||||
* conversion.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param channel Input channel selection.
|
||||
*/
|
||||
void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel);
|
||||
|
||||
/*!
|
||||
* @brief Enable hardware average function and set hardware average number.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param avgNum Hardware average number (see @ref _adc_average_number enumeration).
|
||||
* If avgNum is equal to adcAvgNumNone, it means disable hardware
|
||||
* average function.
|
||||
*/
|
||||
void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum);
|
||||
|
||||
/*!
|
||||
* @brief Set conversion resolution mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param mode resolution mode (see @ref _adc_resolution_mode enumeration).
|
||||
*/
|
||||
static inline void ADC_SetResolutionMode(ADC_Type* base, uint8_t mode)
|
||||
{
|
||||
assert(mode <= adcResolutionBit12);
|
||||
|
||||
ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_MODE_MASK)) |
|
||||
ADC_CFG_MODE(mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set conversion resolution mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Resolution mode (see @ref _adc_resolution_mode enumeration).
|
||||
*/
|
||||
static inline uint8_t ADC_GetResolutionMode(ADC_Type* base)
|
||||
{
|
||||
return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_MODE_MASK) >> ADC_CFG_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set conversion disabled.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
*/
|
||||
void ADC_StopConvert(ADC_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Get right aligned conversion result.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @return Conversion result.
|
||||
*/
|
||||
uint16_t ADC_GetConvertResult(ADC_Type* base);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name ADC Comparer Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable compare function and set the compare work mode of ADC module.
|
||||
* If cmpMode is equal to adcCmpModeDisable, it means to disable the compare function.
|
||||
* @param base ADC base pointer.
|
||||
* @param cmpMode Comparer work mode selected (see @ref _adc_compare_mode enumeration).
|
||||
* - adcCmpModeLessThanCmpVal1: only set compare value 1;
|
||||
* - adcCmpModeGreaterThanCmpVal1: only set compare value 1;
|
||||
* - adcCmpModeOutRangNotInclusive: set compare value 1 less than or equal to compare value 2;
|
||||
* - adcCmpModeInRangNotInclusive: set compare value 1 greater than compare value 2;
|
||||
* - adcCmpModeInRangInclusive: set compare value 1 less than or equal to compare value 2;
|
||||
* - adcCmpModeOutRangInclusive: set compare value 1 greater than compare value 2;
|
||||
* - adcCmpModeDisable: unnecessary to set compare value 1 and compare value 2.
|
||||
* @param cmpVal1 Compare threshold 1.
|
||||
* @param cmpVal2 Compare threshold 2.
|
||||
*/
|
||||
void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Offset Correction Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set ADC module offset correct mode.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param correctMode Offset correct mode.
|
||||
* - true: The offset value is subtracted from the raw converted value;
|
||||
* - false: The offset value is added with the raw result.
|
||||
*/
|
||||
void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode);
|
||||
|
||||
/*!
|
||||
* @brief Set ADC module offset value.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param val Offset value.
|
||||
*/
|
||||
static inline void ADC_SetOffsetVal(ADC_Type* base, uint16_t val)
|
||||
{
|
||||
ADC_OFS_REG(base) = (ADC_OFS_REG(base) & (~ADC_OFS_OFS_MASK)) |
|
||||
ADC_OFS_OFS(val);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Interrupt and Flag Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables ADC conversion complete interrupt request.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param enable Enable/Disable ADC conversion complete interrupt.
|
||||
* - true: Enable conversion complete interrupt.
|
||||
* - false: Disable conversion complete interrupt.
|
||||
*/
|
||||
void ADC_SetIntCmd(ADC_Type* base, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Gets the ADC module conversion complete status flag state.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @retval true: A conversion is completed.
|
||||
* @retval false: A conversion is not completed.
|
||||
*/
|
||||
bool ADC_IsConvertComplete(ADC_Type* base);
|
||||
|
||||
/*!
|
||||
* @brief Gets the ADC module general status flag state.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration).
|
||||
* @return ADC status, each bit represents one status flag.
|
||||
*/
|
||||
static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags)
|
||||
{
|
||||
return (uint32_t)(ADC_GS_REG(base) & flags);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear one or more ADC status flag state.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration).
|
||||
*/
|
||||
static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags)
|
||||
{
|
||||
assert(flags < adcFlagConvertActive);
|
||||
ADC_GS_REG(base) = flags;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name DMA Control Functions.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable or Disable DMA request.
|
||||
*
|
||||
* @param base ADC base pointer.
|
||||
* @param enable Enable/Disable ADC DMA request.
|
||||
* - true: Enable DMA request.
|
||||
* - false: Disable DMA request.
|
||||
*/
|
||||
void ADC_SetDmaCmd(ADC_Type* base, bool enable);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __ADC_IMX6SX_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
192
ext/hal/nxp/imx/drivers/ccm_analog_imx6sx.c
Executable file
192
ext/hal/nxp/imx/drivers/ccm_analog_imx6sx.c
Executable file
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "ccm_analog_imx6sx.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_ANALOG_PowerUpPll
|
||||
* Description : Power up PLL.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl)
|
||||
{
|
||||
/* Judge PLL_USB1 and PLL_USB2 according to register offset value.
|
||||
Because the definition of power control bit is different from the other PLL.*/
|
||||
if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20))
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl);
|
||||
else
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_ANALOG_PowerDownPll
|
||||
* Description : Power down PLL.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl)
|
||||
{
|
||||
/* Judge PLL_USB1 and PLL_USB2 according to register offset value.
|
||||
Because the definition of power control bit is different from the other PLL.*/
|
||||
if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20))
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl);
|
||||
else
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_ANALOG_SetPllBypass
|
||||
* Description : PLL bypass setting.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass)
|
||||
{
|
||||
if(bypass)
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK;
|
||||
else
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_ANALOG_GetPllFreq
|
||||
* Description : Get PLL frequency
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl)
|
||||
{
|
||||
uint8_t divSelect;
|
||||
float numerator, denomitor;
|
||||
uint32_t hz = 0;
|
||||
|
||||
if (CCM_ANALOG_IsPllBypassed(base, pllControl))
|
||||
return 24000000;
|
||||
|
||||
switch(CCM_ANALOG_TUPLE_OFFSET(pllControl))
|
||||
{
|
||||
/* Get PLL_ARM frequency. */
|
||||
case 0x0:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
|
||||
hz = 24000000 * divSelect / 2;
|
||||
break;
|
||||
}
|
||||
/* Get PLL_USB1(PLL3) frequency. */
|
||||
case 0x10:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK;
|
||||
if(divSelect == 0)
|
||||
hz = 480000000;
|
||||
else if(divSelect == 1)
|
||||
hz = 528000000;
|
||||
break;
|
||||
}
|
||||
/* Get PLL_USB2 frequency. */
|
||||
case 0x20:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK;
|
||||
if(divSelect == 0)
|
||||
hz = 480000000;
|
||||
else if(divSelect == 1)
|
||||
hz = 528000000;
|
||||
break;
|
||||
}
|
||||
/* Get PLL_SYS(PLL2) frequency. */
|
||||
case 0x30:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK;
|
||||
if(divSelect == 0)
|
||||
hz = 480000000;
|
||||
else
|
||||
hz = 528000000;
|
||||
break;
|
||||
}
|
||||
/* Get PLL_AUDIO frequency. */
|
||||
case 0x70:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK;
|
||||
numerator = CCM_ANALOG_PLL_AUDIO_NUM & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK;
|
||||
denomitor = CCM_ANALOG_PLL_AUDIO_DENOM & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK;
|
||||
hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor)));
|
||||
break;
|
||||
}
|
||||
/* Get PLL_VIDEO frequency. */
|
||||
case 0xA0:
|
||||
{
|
||||
divSelect = CCM_ANALOG_PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK;
|
||||
numerator = CCM_ANALOG_PLL_VIDEO_NUM & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK;
|
||||
denomitor = CCM_ANALOG_PLL_VIDEO_DENOM & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK;
|
||||
hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor)));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return hz;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_ANALOG_GetPfdFreq
|
||||
* Description : Get PFD frequency
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac)
|
||||
{
|
||||
uint32_t main, frac;
|
||||
|
||||
/* Judge whether pfdFrac is PLL2 PFD or not. */
|
||||
if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0x100)
|
||||
{
|
||||
/* PFD should work with PLL2 without bypass */
|
||||
assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllSysControl));
|
||||
main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllSysControl);
|
||||
}
|
||||
else if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0xF0)
|
||||
{
|
||||
/* PFD should work with PLL3 without bypass */
|
||||
assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllUsb1Control));
|
||||
main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllUsb1Control);
|
||||
}
|
||||
else
|
||||
main = 0;
|
||||
|
||||
frac = CCM_ANALOG_GetPfdFrac(base, pfdFrac);
|
||||
|
||||
return main / frac * 18;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
340
ext/hal/nxp/imx/drivers/ccm_analog_imx6sx.h
Executable file
340
ext/hal/nxp/imx/drivers/ccm_analog_imx6sx.h
Executable file
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CCM_ANALOG_IMX6SX_H__
|
||||
#define __CCM_ANALOG_IMX6SX_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <assert.h>
|
||||
#include "device_imx.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ccm_analog_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define CCM_ANALOG_TUPLE(reg, shift) ((offsetof(CCM_ANALOG_Type, reg) & 0xFFFF) | ((shift) << 16))
|
||||
#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFFFF) + off)))
|
||||
#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0)
|
||||
#define CCM_ANALOG_TUPLE_REG_SET(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 4)
|
||||
#define CCM_ANALOG_TUPLE_REG_CLR(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 8)
|
||||
#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((tuple) >> 16) & 0x1F)
|
||||
#define CCM_ANALOG_TUPLE_OFFSET(tuple) ((tuple) & 0xFFFF)
|
||||
|
||||
/*!
|
||||
* @brief PLL control names for PLL power/bypass/lock/frequency operations.
|
||||
*
|
||||
* These constants define the PLL control names for PLL power/bypass/lock operations.\n
|
||||
* - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
|
||||
* - 16:20: Powerdown/Power bit shift.
|
||||
*/
|
||||
enum _ccm_analog_pll_control
|
||||
{
|
||||
ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/
|
||||
ccmAnalogPllUsb1Control = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_POWER_SHIFT), /*!< CCM Analog USB1 PLL Control.*/
|
||||
ccmAnalogPllUsb2Control = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_POWER_SHIFT), /*!< CCM Analog USB2 PLL Control.*/
|
||||
ccmAnalogPllSysControl = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT), /*!< CCM Analog SYSTEM PLL Control.*/
|
||||
ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/
|
||||
ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/
|
||||
ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog ETHERNET PLL Control.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief PLL clock names for clock enable/disable settings.
|
||||
*
|
||||
* These constants define the PLL clock names for PLL clock enable/disable operations.\n
|
||||
* - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
|
||||
* - 16:20: Clock enable bit shift.
|
||||
*/
|
||||
enum _ccm_analog_pll_clock
|
||||
{
|
||||
ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< CCM Analog ARM PLL Clock.*/
|
||||
ccmAnalogPllUsb1Clock = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< CCM Analog USB1 PLL Clock.*/
|
||||
ccmAnalogPllUsb2Clock = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< CCM Analog USB2 PLL Clock.*/
|
||||
ccmAnalogPllSysClock = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< CCM Analog SYSTEM PLL Clock.*/
|
||||
ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/
|
||||
ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/
|
||||
ccmAnalogPllEnetClock25Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< CCM Analog ETHERNET 25MHz PLL Clock.*/
|
||||
ccmAnalogPllEnet2Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT), /*!< CCM Analog ETHERNET2 125MHz PLL Clock.*/
|
||||
ccmAnalogPllEnet1Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT), /*!< CCM Analog ETHERNET1 125MHz PLL Clock.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief PFD gate names for clock gate settings, clock source is PLL2 and PLL3
|
||||
*
|
||||
* These constants define the PFD gate names for PFD clock enable/disable operations.\n
|
||||
* - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
|
||||
* - 16:20: Clock gate bit shift.
|
||||
*/
|
||||
enum _ccm_analog_pfd_clkgate
|
||||
{
|
||||
ccmAnalogPll2Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD0 Clock Gate.*/
|
||||
ccmAnalogPll2Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD1 Clock Gate.*/
|
||||
ccmAnalogPll2Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD2 Clock Gate.*/
|
||||
ccmAnalogPll2Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD3 Clock Gate.*/
|
||||
ccmAnalogPll3Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD0 Clock Gate.*/
|
||||
ccmAnalogPll3Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD1 Clock Gate.*/
|
||||
ccmAnalogPll3Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD2 Clock Gate.*/
|
||||
ccmAnalogPll3Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD3 Clock Gate.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief PFD fraction names for clock fractional divider operations.
|
||||
*
|
||||
* These constants define the PFD fraction names for PFD fractional divider operations.\n
|
||||
* - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
|
||||
* - 16:20: Fraction bits shift
|
||||
*/
|
||||
enum _ccm_analog_pfd_frac
|
||||
{
|
||||
ccmAnalogPll2Pfd0Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD0 fractional divider.*/
|
||||
ccmAnalogPll2Pfd1Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD1 fractional divider.*/
|
||||
ccmAnalogPll2Pfd2Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD2 fractional divider.*/
|
||||
ccmAnalogPll2Pfd3Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD3 fractional divider.*/
|
||||
ccmAnalogPll3Pfd0Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD0 fractional divider.*/
|
||||
ccmAnalogPll3Pfd1Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD1 fractional divider.*/
|
||||
ccmAnalogPll3Pfd2Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD2 fractional divider.*/
|
||||
ccmAnalogPll3Pfd3Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD3 fractional divider.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief PFD stable names for clock stable query
|
||||
*
|
||||
* These constants define the PFD stable names for clock stable query.\n
|
||||
* - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
|
||||
* - 16:20: Stable bit shift.
|
||||
*/
|
||||
enum _ccm_analog_pfd_stable
|
||||
{
|
||||
ccmAnalogPll2Pfd0Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD0 clock stable query.*/
|
||||
ccmAnalogPll2Pfd1Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD1 clock stable query.*/
|
||||
ccmAnalogPll2Pfd2Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD2 clock stable query.*/
|
||||
ccmAnalogPll2Pfd3Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD3 clock stable query.*/
|
||||
ccmAnalogPll3Pfd0Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD0 clock stable query.*/
|
||||
ccmAnalogPll3Pfd1Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD1 clock stable query.*/
|
||||
ccmAnalogPll3Pfd2Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD2 clock stable query.*/
|
||||
ccmAnalogPll3Pfd3Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD3 clock stable query.*/
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name CCM Analog PLL Operation Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Power up PLL
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
*/
|
||||
void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl);
|
||||
|
||||
/*!
|
||||
* @brief Power down PLL
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
*/
|
||||
void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl);
|
||||
|
||||
/*!
|
||||
* @brief PLL bypass setting
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
* @param bypass Bypass the PLL.
|
||||
* - true: Bypass the PLL.
|
||||
* - false: Do not bypass the PLL.
|
||||
*/
|
||||
void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass);
|
||||
|
||||
/*!
|
||||
* @brief Check if PLL is bypassed
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
* @return PLL bypass status.
|
||||
* - true: The PLL is bypassed.
|
||||
* - false: The PLL is not bypassed.
|
||||
*/
|
||||
static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl)
|
||||
{
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_BYPASS_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Check if PLL clock is locked
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
* @return PLL lock status.
|
||||
* - true: The PLL is locked.
|
||||
* - false: The PLL is not locked.
|
||||
*/
|
||||
static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl)
|
||||
{
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_LOCK_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable PLL clock
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration)
|
||||
*/
|
||||
static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock)
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable PLL clock
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration)
|
||||
*/
|
||||
static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock)
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get PLL(involved all PLLs) clock frequency.
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration)
|
||||
* @return PLL clock frequency in HZ.
|
||||
*/
|
||||
uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name CCM Analog PFD Operation Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable PFD clock
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration)
|
||||
*/
|
||||
static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate)
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable PFD clock
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration)
|
||||
*/
|
||||
static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate)
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Check if PFD clock is stable
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration)
|
||||
* @return PFD clock stable status.
|
||||
* - true: The PFD clock is stable.
|
||||
* - false: The PFD clock is not stable.
|
||||
*/
|
||||
static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable)
|
||||
{
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pfdStable) & (1 << CCM_ANALOG_TUPLE_SHIFT(pfdStable)));
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Set PFD clock fraction
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration)
|
||||
* @param value PFD clock fraction value
|
||||
*/
|
||||
static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value)
|
||||
{
|
||||
assert(value >= 12 && value <= 35);
|
||||
CCM_ANALOG_TUPLE_REG_CLR(base, pfdFrac) = CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK << CCM_ANALOG_TUPLE_SHIFT(pfdFrac);
|
||||
CCM_ANALOG_TUPLE_REG_SET(base, pfdFrac) = value << CCM_ANALOG_TUPLE_SHIFT(pfdFrac);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get PFD clock fraction
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration)
|
||||
* @return PFD clock fraction value
|
||||
*/
|
||||
static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac)
|
||||
{
|
||||
return (CCM_ANALOG_TUPLE_REG(base, pfdFrac) >> CCM_ANALOG_TUPLE_SHIFT(pfdFrac)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get PFD clock frequency
|
||||
*
|
||||
* @param base CCM_ANALOG base pointer.
|
||||
* @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration)
|
||||
* @return PFD clock frequency in HZ
|
||||
*/
|
||||
uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __CCM_ANALOG_IMX6SX_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
67
ext/hal/nxp/imx/drivers/ccm_imx6sx.c
Executable file
67
ext/hal/nxp/imx/drivers/ccm_imx6sx.c
Executable file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "ccm_imx6sx.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_SetClockEnableSignalOverrided
|
||||
* Description : Override or do not override clock enable signal from module.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control)
|
||||
{
|
||||
if(control)
|
||||
CCM_CMEOR_REG(base) |= signal;
|
||||
else
|
||||
CCM_CMEOR_REG(base) &= ~signal;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CCM_SetMmdcHandshakeMask
|
||||
* Description : Set handshake mask of MMDC module.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask)
|
||||
{
|
||||
if(mask)
|
||||
CCM_CCDR_REG(base) |= CCM_CCDR_mmdc_mask_MASK;
|
||||
else
|
||||
CCM_CCDR_REG(base) &= ~CCM_CCDR_mmdc_mask_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
785
ext/hal/nxp/imx/drivers/ccm_imx6sx.h
Executable file
785
ext/hal/nxp/imx/drivers/ccm_imx6sx.h
Executable file
|
|
@ -0,0 +1,785 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CCM_IMX6SX_H__
|
||||
#define __CCM_IMX6SX_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <assert.h>
|
||||
#include "device_imx.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ccm_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define CCM_TUPLE(reg, shift, mask) ((offsetof(CCM_Type, reg) & 0xFF) | ((shift) << 8) | (((mask >> shift) & 0xFFFF) << 16))
|
||||
#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFF))))
|
||||
#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8) & 0x1F)
|
||||
#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 16) & 0xFFFF) << ((((tuple) >> 8) & 0x1F))))
|
||||
|
||||
/*!
|
||||
* @brief Root control names for root clock setting.
|
||||
*
|
||||
* These constants define the root control names for root clock setting.\n
|
||||
* - 0:7: REG offset to CCM_BASE in bytes.
|
||||
* - 8:15: Root clock setting bit field shift.
|
||||
* - 16:31: Root clock setting bit field width.
|
||||
*/
|
||||
enum _ccm_root_clock_control
|
||||
{
|
||||
ccmRootPll1SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll1_sw_clk_sel_SHIFT, CCM_CCSR_pll1_sw_clk_sel_MASK), /*!< PLL1 SW Clock control name.*/
|
||||
ccmRootStepSel = CCM_TUPLE(CCSR, CCM_CCSR_step_sel_SHIFT, CCM_CCSR_step_sel_MASK), /*!< Step SW Clock control name.*/
|
||||
ccmRootPeriph2ClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk_sel_SHIFT, CCM_CBCDR_periph2_clk_sel_MASK), /*!< Peripheral2 Clock control name.*/
|
||||
ccmRootPrePeriph2ClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph2_clk_sel_SHIFT, CCM_CBCMR_pre_periph2_clk_sel_MASK), /*!< Pre Peripheral2 Clock control name.*/
|
||||
ccmRootPeriph2Clk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph2_clk2_sel_SHIFT, CCM_CBCMR_periph2_clk2_sel_MASK), /*!< Peripheral2 Clock2 Clock control name.*/
|
||||
ccmRootPll3SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll3_sw_clk_sel_SHIFT, CCM_CCSR_pll3_sw_clk_sel_MASK), /*!< PLL3 SW Clock control name.*/
|
||||
ccmRootOcramClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_clk_sel_SHIFT, CCM_CBCDR_ocram_clk_sel_MASK), /*!< OCRAM Clock control name.*/
|
||||
ccmRootOcramAltClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_alt_clk_sel_SHIFT, CCM_CBCDR_ocram_alt_clk_sel_MASK), /*!< OCRAM ALT Clock control name.*/
|
||||
ccmRootPeriphClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk_sel_SHIFT, CCM_CBCDR_periph_clk_sel_MASK), /*!< Peripheral Clock control name.*/
|
||||
ccmRootPeriphClk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph_clk2_sel_SHIFT, CCM_CBCMR_periph_clk2_sel_MASK), /*!< Peripheral Clock2 control name.*/
|
||||
ccmRootPrePeriphClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph_clk_sel_SHIFT, CCM_CBCMR_pre_periph_clk_sel_MASK), /*!< Pre Peripheral Clock control name.*/
|
||||
ccmRootPcieAxiClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pcie_axi_clk_sel_SHIFT, CCM_CBCMR_pcie_axi_clk_sel_MASK), /*!< PCIE AXI Clock control name.*/
|
||||
ccmRootPerclkClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_clk_sel_SHIFT, CCM_CSCMR1_perclk_clk_sel_MASK), /*!< Pre Clock control name.*/
|
||||
ccmRootUsdhc1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc1_clk_sel_SHIFT, CCM_CSCMR1_usdhc1_clk_sel_MASK), /*!< USDHC1 Clock control name.*/
|
||||
ccmRootUsdhc2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc2_clk_sel_SHIFT, CCM_CSCMR1_usdhc2_clk_sel_MASK), /*!< USDHC2 Clock control name.*/
|
||||
ccmRootUsdhc3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc3_clk_sel_SHIFT, CCM_CSCMR1_usdhc3_clk_sel_MASK), /*!< USDHC3 Clock control name.*/
|
||||
ccmRootUsdhc4ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc4_clk_sel_SHIFT, CCM_CSCMR1_usdhc4_clk_sel_MASK), /*!< USDHC4 Clock control name.*/
|
||||
ccmRootAclkEimSlowSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_sel_SHIFT, CCM_CSCMR1_aclk_eim_slow_sel_MASK), /*!< ACLK EIM SLOW Clock control name.*/
|
||||
ccmRootGpuAxiSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_sel_SHIFT, CCM_CBCMR_gpu_axi_sel_MASK), /*!< GPU AXI Clock control name.*/
|
||||
ccmRootGpuCoreSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_sel_SHIFT, CCM_CBCMR_gpu_core_sel_MASK), /*!< GPU Core Clock control name.*/
|
||||
ccmRootVidClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_sel_SHIFT, CCM_CSCMR2_vid_clk_sel_MASK), /*!< VID Clock control name.*/
|
||||
ccmRootEsaiClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_esai_clk_sel_SHIFT, CCM_CSCMR2_esai_clk_sel_MASK), /*!< ESAI Clock control name.*/
|
||||
ccmRootAudioClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_sel_SHIFT, CCM_CDCDR_audio_clk_sel_MASK), /*!< AUDIO Clock control name.*/
|
||||
ccmRootSpdif0ClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_sel_SHIFT, CCM_CDCDR_spdif0_clk_sel_MASK), /*!< SPDIF0 Clock control name.*/
|
||||
ccmRootSsi1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi1_clk_sel_SHIFT, CCM_CSCMR1_ssi1_clk_sel_MASK), /*!< SSI1 Clock control name.*/
|
||||
ccmRootSsi2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi2_clk_sel_SHIFT, CCM_CSCMR1_ssi2_clk_sel_MASK), /*!< SSI2 Clock control name.*/
|
||||
ccmRootSsi3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi3_clk_sel_SHIFT, CCM_CSCMR1_ssi3_clk_sel_MASK), /*!< SSI3 Clock control name.*/
|
||||
ccmRootLcdif2ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_clk_sel_MASK), /*!< LCDIF2 Clock control name.*/
|
||||
ccmRootLcdif2PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_pre_clk_sel_MASK), /*!< LCDIF2 Pre Clock control name.*/
|
||||
ccmRootLdbDi1ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di1_clk_sel_SHIFT, CCM_CS2CDR_ldb_di1_clk_sel_MASK), /*!< LDB DI1 Clock control name.*/
|
||||
ccmRootLdbDi0ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di0_clk_sel_SHIFT, CCM_CS2CDR_ldb_di0_clk_sel_MASK), /*!< LDB DI0 Clock control name.*/
|
||||
ccmRootLcdif1ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_clk_sel_MASK), /*!< LCDIF1 Clock control name.*/
|
||||
ccmRootLcdif1PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_pre_clk_sel_MASK), /*!< LCDIF1 Pre Clock control name.*/
|
||||
ccmRootM4ClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_clk_sel_SHIFT, CCM_CHSCCDR_m4_clk_sel_MASK), /*!< M4 Clock control name.*/
|
||||
ccmRootM4PreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_pre_clk_sel_SHIFT, CCM_CHSCCDR_m4_pre_clk_sel_MASK), /*!< M4 Pre Clock control name.*/
|
||||
ccmRootEnetClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_clk_sel_SHIFT, CCM_CHSCCDR_enet_clk_sel_MASK), /*!< Ethernet Clock control name.*/
|
||||
ccmRootEnetPreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_pre_clk_sel_SHIFT, CCM_CHSCCDR_enet_pre_clk_sel_MASK), /*!< Ethernet Pre Clock control name.*/
|
||||
ccmRootQspi2ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_sel_SHIFT, CCM_CS2CDR_qspi2_clk_sel_MASK), /*!< QSPI2 Clock control name.*/
|
||||
ccmRootDisplayClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_clk_sel_SHIFT, CCM_CSCDR3_display_clk_sel_MASK), /*!< Display Clock control name.*/
|
||||
ccmRootCsiClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_clk_sel_SHIFT, CCM_CSCDR3_csi_clk_sel_MASK), /*!< CSI Clock control name.*/
|
||||
ccmRootCanClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_sel_SHIFT, CCM_CSCMR2_can_clk_sel_MASK), /*!< CAN Clock control name.*/
|
||||
ccmRootEcspiClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_sel_SHIFT, CCM_CSCDR2_ecspi_clk_sel_MASK), /*!< ECSPI Clock control name.*/
|
||||
ccmRootUartClkSel = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_sel_SHIFT, CCM_CSCDR1_uart_clk_sel_MASK) /*!< UART Clock control name.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for pll1_sw_clk_sel. */
|
||||
enum _ccm_rootmux_pll1_sw_clk_sel
|
||||
{
|
||||
ccmRootmuxPll1SwClkPll1MainClk = 0U, /*!< PLL1 SW Clock from PLL1 Main Clock.*/
|
||||
ccmRootmuxPll1SwClkStepClk = 1U, /*!< PLL1 SW Clock from Step Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for step_sel. */
|
||||
enum _ccm_rootmux_step_sel
|
||||
{
|
||||
ccmRootmuxStepOsc24m = 0U, /*!< Step Clock from OSC 24M.*/
|
||||
ccmRootmuxStepPll2Pfd2 = 1U, /*!< Step Clock from PLL2 PFD2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for periph2_clk_sel. */
|
||||
enum _ccm_rootmux_periph2_clk_sel
|
||||
{
|
||||
ccmRootmuxPeriph2ClkPrePeriph2Clk = 0U, /*!< Peripheral2 Clock from Pre Peripheral2 Clock.*/
|
||||
ccmRootmuxPeriph2ClkPeriph2Clk2 = 1U, /*!< Peripheral2 Clock from Peripheral2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for pre_periph2_clk_sel. */
|
||||
enum _ccm_rootmux_pre_periph2_clk_sel
|
||||
{
|
||||
ccmRootmuxPrePeriph2ClkPll2 = 0U, /*!< Pre Peripheral2 Clock from PLL2.*/
|
||||
ccmRootmuxPrePeriph2ClkPll2Pfd2 = 1U, /*!< Pre Peripheral2 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxPrePeriph2ClkPll2Pfd0 = 2U, /*!< Pre Peripheral2 Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxPrePeriph2ClkPll4 = 3U, /*!< Pre Peripheral2 Clock from PLL4.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for periph2_clk2_sel. */
|
||||
enum _ccm_rootmux_periph2_clk2_sel
|
||||
{
|
||||
ccmRootmuxPeriph2Clk2Pll3SwClk = 0U, /*!< Peripheral2 Clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxPeriph2Clk2Osc24m = 1U, /*!< Peripheral2 Clock from OSC 24M.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for pll3_sw_clk_sel. */
|
||||
enum _ccm_rootmux_pll3_sw_clk_sel
|
||||
{
|
||||
ccmRootmuxPll3SwClkPll3 = 0U, /*!< PLL3 SW Clock from PLL3.*/
|
||||
ccmRootmuxPll3SwClkPll3BypassClk = 1U, /*!< PLL3 SW Clock from PLL3 Bypass Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ocram_clk_sel. */
|
||||
enum _ccm_rootmux_ocram_clk_sel
|
||||
{
|
||||
ccmRootmuxOcramClkPeriphClk = 0U, /*!< OCRAM Clock from Peripheral Clock.*/
|
||||
ccmRootmuxOcramClkOcramAltClk = 1U, /*!< OCRAM Clock from OCRAM ALT Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ocram_alt_clk_sel. */
|
||||
enum _ccm_rootmux_ocram_alt_clk_sel
|
||||
{
|
||||
ccmRootmuxOcramAltClkPll2Pfd2 = 0U, /*!< OCRAM ALT Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxOcramAltClkPll3Pfd1 = 1U, /*!< OCRAM ALT Clock from PLL3 PFD1.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for periph_clk_sel. */
|
||||
enum _ccm_rootmux_periph_clk_sel
|
||||
{
|
||||
ccmRootmuxPeriphClkPrePeriphClkSel = 0U, /*!< Peripheral Clock from Pre Peripheral .*/
|
||||
ccmRootmuxPeriphClkPeriphClk2Sel = 1U, /*!< Peripheral Clock from Peripheral2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for periph_clk2_sel. */
|
||||
enum _ccm_rootmux_periph_clk2_sel
|
||||
{
|
||||
ccmRootmuxPeriphClk2Pll3SwClk = 0U, /*!< Peripheral Clock2 from from PLL3 SW Clock.*/
|
||||
ccmRootmuxPeriphClk2OSC24m = 1U, /*!< Peripheral Clock2 from OSC 24M.*/
|
||||
ccmRootmuxPeriphClk2Pll2 = 2U, /*!< Peripheral Clock2 from PLL2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for pre_periph_clk_sel. */
|
||||
enum _ccm_rootmux_pre_periph_clk_sel
|
||||
{
|
||||
ccmRootmuxPrePeriphClkPll2 = 0U, /*!< Pre Peripheral Clock from PLL2.*/
|
||||
ccmRootmuxPrePeriphClkPll2Pfd2 = 1U, /*!< Pre Peripheral Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxPrePeriphClkPll2Pfd0 = 2U, /*!< Pre Peripheral Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxPrePeriphClkPll2Pfd2div2 = 3U, /*!< Pre Peripheral Clock from PLL2 PFD2 divided by 2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for pcie_axi_clk_sel. */
|
||||
enum _ccm_rootmux_pcie_axi_clk_sel
|
||||
{
|
||||
ccmRootmuxPcieAxiClkAxiClk = 0U, /*!< PCIE AXI Clock from AXI Clock.*/
|
||||
ccmRootmuxPcieAxiClkAhbClk = 1U, /*!< PCIE AXI Clock from AHB Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for perclk_clk_sel. */
|
||||
enum _ccm_rootmux_perclk_clk_sel
|
||||
{
|
||||
ccmRootmuxPerclkClkIpgClkRoot = 0U, /*!< Perclk from IPG Clock Root.*/
|
||||
ccmRootmuxPerclkClkOsc24m = 1U, /*!< Perclk from OSC 24M.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for usdhc1_clk_sel. */
|
||||
enum _ccm_rootmux_usdhc1_clk_sel
|
||||
{
|
||||
ccmRootmuxUsdhc1ClkPll2Pfd2 = 0U, /*!< USDHC1 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxUsdhc1ClkPll2Pfd0 = 1U, /*!< USDHC1 Clock from PLL2 PFD0.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for usdhc2_clk_sel. */
|
||||
enum _ccm_rootmux_usdhc2_clk_sel
|
||||
{
|
||||
ccmRootmuxUsdhc2ClkPll2Pfd2 = 0U, /*!< USDHC2 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxUsdhc2ClkPll2Pfd0 = 1U, /*!< USDHC2 Clock from PLL2 PFD0.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for usdhc3_clk_sel. */
|
||||
enum _ccm_rootmux_usdhc3_clk_sel
|
||||
{
|
||||
ccmRootmuxUsdhc3ClkPll2Pfd2 = 0U, /*!< USDHC3 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxUsdhc3ClkPll2Pfd0 = 1U, /*!< USDHC3 Clock from PLL2 PFD0.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for usdhc4_clk_sel. */
|
||||
enum _ccm_rootmux_usdhc4_clk_sel
|
||||
{
|
||||
ccmRootmuxUsdhc4ClkPll2Pfd2 = 0U, /*!< USDHC4 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxUsdhc4ClkPll2Pfd0 = 1U, /*!< USDHC4 Clock from PLL2 PFD0.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for aclk_eim_slow_sel. */
|
||||
enum _ccm_rootmux_aclk_eim_slow_sel
|
||||
{
|
||||
ccmRootmuxAclkEimSlowAxiClk = 0U, /*!< Aclk EimSlow Clock from AXI Clock.*/
|
||||
ccmRootmuxAclkEimSlowPll3SwClk = 1U, /*!< Aclk EimSlow Clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxAclkEimSlowPll2Pfd2 = 2U, /*!< Aclk EimSlow Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxAclkEimSlowPll3Pfd0 = 3U, /*!< Aclk EimSlow Clock from PLL3 PFD0.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for gpu_axi_sel. */
|
||||
enum _ccm_rootmux_gpu_axi_sel
|
||||
{
|
||||
ccmRootmuxGpuAxiPll2Pfd2 = 0U, /*!< GPU AXI Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxGpuAxiPll3Pfd0 = 1U, /*!< GPU AXI Clock from PLL3 PFD0.*/
|
||||
ccmRootmuxGpuAxiPll2Pfd1 = 2U, /*!< GPU AXI Clock from PLL2 PFD1.*/
|
||||
ccmRootmuxGpuAxiPll2 = 3U, /*!< GPU AXI Clock from PLL2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for gpu_core_sel. */
|
||||
enum _ccm_rootmux_gpu_core_sel
|
||||
{
|
||||
ccmRootmuxGpuCorePll3Pfd1 = 0U, /*!< GPU Core Clock from PLL3 PFD1.*/
|
||||
ccmRootmuxGpuCorePll3Pfd0 = 1U, /*!< GPU Core Clock from PLL3 PFD0.*/
|
||||
ccmRootmuxGpuCorePll2 = 2U, /*!< GPU Core Clock from PLL2.*/
|
||||
ccmRootmuxGpuCorePll2Pfd2 = 3U, /*!< GPU Core Clock from PLL2 PFD2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for vid_clk_sel. */
|
||||
enum _ccm_rootmux_vid_clk_sel
|
||||
{
|
||||
ccmRootmuxVidClkPll3Pfd1 = 0U, /*!< VID Clock from PLL3 PFD1.*/
|
||||
ccmRootmuxVidClkPll3 = 1U, /*!< VID Clock from PLL3.*/
|
||||
ccmRootmuxVidClkPll3Pfd3 = 2U, /*!< VID Clock from PLL3 PFD3.*/
|
||||
ccmRootmuxVidClkPll4 = 3U, /*!< VID Clock from PLL4.*/
|
||||
ccmRootmuxVidClkPll5 = 4U, /*!< VID Clock from PLL5.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for esai_clk_sel. */
|
||||
enum _ccm_rootmux_esai_clk_sel
|
||||
{
|
||||
ccmRootmuxEsaiClkPll4 = 0U, /*!< ESAI Clock from PLL4.*/
|
||||
ccmRootmuxEsaiClkPll3Pfd2 = 1U, /*!< ESAI Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxEsaiClkPll5 = 2U, /*!< ESAI Clock from PLL5.*/
|
||||
ccmRootmuxEsaiClkPll3SwClk = 3U, /*!< ESAI Clock from PLL3 SW Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for audio_clk_sel. */
|
||||
enum _ccm_rootmux_audio_clk_sel
|
||||
{
|
||||
ccmRootmuxAudioClkPll4 = 0U, /*!< Audio Clock from PLL4.*/
|
||||
ccmRootmuxAudioClkPll3Pfd2 = 1U, /*!< Audio Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxAudioClkPll5 = 2U, /*!< Audio Clock from PLL5.*/
|
||||
ccmRootmuxAudioClkPll3SwClk = 3U, /*!< Audio Clock from PLL3 SW Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for spdif0_clk_sel. */
|
||||
enum _ccm_rootmux_spdif0_clk_sel
|
||||
{
|
||||
ccmRootmuxSpdif0ClkPll4 = 0U, /*!< SPDIF0 Clock from PLL4.*/
|
||||
ccmRootmuxSpdif0ClkPll3Pfd2 = 1U, /*!< SPDIF0 Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxSpdif0ClkPll5 = 2U, /*!< SPDIF0 Clock from PLL5.*/
|
||||
ccmRootmuxSpdif0ClkPll3SwClk = 3U, /*!< SPDIF0 Clock from PLL3 SW Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ssi1_clk_sel. */
|
||||
enum _ccm_rootmux_ssi1_clk_sel
|
||||
{
|
||||
ccmRootmuxSsi1ClkPll3Pfd2 = 0U, /*!< SSI1 Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxSsi1ClkPll5 = 1U, /*!< SSI1 Clock from PLL5.*/
|
||||
ccmRootmuxSsi1ClkPll4 = 2U, /*!< SSI1 Clock from PLL4.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ssi2_clk_sel. */
|
||||
enum _ccm_rootmux_ssi2_clk_sel
|
||||
{
|
||||
ccmRootmuxSsi2ClkPll3Pfd2 = 0U, /*!< SSI2 Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxSsi2ClkPll5 = 1U, /*!< SSI2 Clock from PLL5.*/
|
||||
ccmRootmuxSsi2ClkPll4 = 2U, /*!< SSI2 Clock from PLL4.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ssi3_clk_sel. */
|
||||
enum _ccm_rootmux_ssi3_clk_sel
|
||||
{
|
||||
ccmRootmuxSsi3ClkPll3Pfd2 = 0U, /*!< SSI3 Clock from PLL3 PFD2.*/
|
||||
ccmRootmuxSsi3ClkPll5 = 1U, /*!< SSI3 Clock from PLL5.*/
|
||||
ccmRootmuxSsi3ClkPll4 = 2U, /*!< SSI3 Clock from PLL4.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for lcdif2_clk_sel. */
|
||||
enum _ccm_rootmux_lcdif2_clk_sel
|
||||
{
|
||||
ccmRootmuxLcdif2ClkLcdif2PreClk = 0U, /*!< LCDIF2 Clock from LCDIF2 Pre Clock.*/
|
||||
ccmRootmuxLcdif2ClkIppDi0Clk = 1U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/
|
||||
ccmRootmuxLcdif2ClkIppDi1Clk = 2U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/
|
||||
ccmRootmuxLcdif2ClkLdbDi0Clk = 3U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/
|
||||
ccmRootmuxLcdif2ClkLdbDi1Clk = 4U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for lcdif2_pre_clk_sel. */
|
||||
enum _ccm_rootmux_lcdif2_pre_clk_sel
|
||||
{
|
||||
ccmRootmuxLcdif2ClkPrePll2 = 0U, /*!< LCDIF2 Pre Clock from PLL2.*/
|
||||
ccmRootmuxLcdif2ClkPrePll3Pfd3 = 1U, /*!< LCDIF2 Pre Clock from PLL3 PFD3.*/
|
||||
ccmRootmuxLcdif2ClkPrePll5 = 2U, /*!< LCDIF2 Pre Clock from PLL3 PFD5.*/
|
||||
ccmRootmuxLcdif2ClkPrePll2Pfd0 = 3U, /*!< LCDIF2 Pre Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxLcdif2ClkPrePll2Pfd3 = 4U, /*!< LCDIF2 Pre Clock from PLL2 PFD3.*/
|
||||
ccmRootmuxLcdif2ClkPrePll3Pfd1 = 5U, /*!< LCDIF2 Pre Clock from PLL3 PFD1.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ldb_di1_clk_sel. */
|
||||
enum _ccm_rootmux_ldb_di1_clk_sel
|
||||
{
|
||||
ccmRootmuxLdbDi1ClkPll3SwClk = 0U, /*!< lDB DI1 Clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxLdbDi1ClkPll2Pfd0 = 1U, /*!< lDB DI1 Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxLdbDi1ClkPll2Pfd2 = 2U, /*!< lDB DI1 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxLdbDi1ClkPll2 = 3U, /*!< lDB DI1 Clock from PLL2.*/
|
||||
ccmRootmuxLdbDi1ClkPll3Pfd3 = 4U, /*!< lDB DI1 Clock from PLL3 PFD3.*/
|
||||
ccmRootmuxLdbDi1ClkPll3Pfd2 = 5U, /*!< lDB DI1 Clock from PLL3 PFD2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ldb_di0_clk_sel. */
|
||||
enum _ccm_rootmux_ldb_di0_clk_sel
|
||||
{
|
||||
ccmRootmuxLdbDi0ClkPll5 = 0U, /*!< lDB DI0 Clock from PLL5.*/
|
||||
ccmRootmuxLdbDi0ClkPll2Pfd0 = 1U, /*!< lDB DI0 Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxLdbDi0ClkPll2Pfd2 = 2U, /*!< lDB DI0 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxLdbDi0ClkPll2Pfd3 = 3U, /*!< lDB DI0 Clock from PLL2 PFD3.*/
|
||||
ccmRootmuxLdbDi0ClkPll3Pfd1 = 4U, /*!< lDB DI0 Clock from PLL3 PFD1.*/
|
||||
ccmRootmuxLdbDi0ClkPll3Pfd3 = 5U, /*!< lDB DI0 Clock from PLL3 PFD3.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for lcdif1_clk_sel. */
|
||||
enum _ccm_rootmux_lcdif1_clk_sel
|
||||
{
|
||||
ccmRootmuxLcdif1ClkLcdif1PreClk = 0U, /*!< LCDIF1 clock from LCDIF1 Pre Clock.*/
|
||||
ccmRootmuxLcdif1ClkIppDi0Clk = 1U, /*!< LCDIF1 clock from IPP DI0 Clock.*/
|
||||
ccmRootmuxLcdif1ClkIppDi1Clk = 2U, /*!< LCDIF1 clock from IPP DI1 Clock.*/
|
||||
ccmRootmuxLcdif1ClkLdbDi0Clk = 3U, /*!< LCDIF1 clock from LDB DI0 Clock.*/
|
||||
ccmRootmuxLcdif1ClkLdbDi1Clk = 4U, /*!< LCDIF1 clock from LDB DI1 Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for lcdif1_pre_clk_sel. */
|
||||
enum _ccm_rootmux_lcdif1_pre_clk_sel
|
||||
{
|
||||
ccmRootmuxLcdif1PreClkPll2 = 0U, /*!< LCDIF1 pre clock from PLL2.*/
|
||||
ccmRootmuxLcdif1PreClkPll3Pfd3 = 1U, /*!< LCDIF1 pre clock from PLL3 PFD3.*/
|
||||
ccmRootmuxLcdif1PreClkPll5 = 2U, /*!< LCDIF1 pre clock from PLL5.*/
|
||||
ccmRootmuxLcdif1PreClkPll2Pfd0 = 3U, /*!< LCDIF1 pre clock from PLL2 PFD0.*/
|
||||
ccmRootmuxLcdif1PreClkPll2Pfd1 = 4U, /*!< LCDIF1 pre clock from PLL2 PFD1.*/
|
||||
ccmRootmuxLcdif1PreClkPll3Pfd1 = 5U, /*!< LCDIF1 pre clock from PLL3 PFD1.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for m4_clk_sel. */
|
||||
enum _ccm_rootmux_m4_clk_sel
|
||||
{
|
||||
ccmRootmuxM4ClkM4PreClk = 0U, /*!< M4 clock from M4 Pre Clock.*/
|
||||
ccmRootmuxM4ClkPll3Pfd3 = 1U, /*!< M4 clock from PLL3 PFD3.*/
|
||||
ccmRootmuxM4ClkIppDi0Clk = 2U, /*!< M4 clock from IPP DI0 Clock.*/
|
||||
ccmRootmuxM4ClkIppDi1Clk = 3U, /*!< M4 clock from IPP DI1 Clock.*/
|
||||
ccmRootmuxM4ClkLdbDi0Clk = 4U, /*!< M4 clock from LDB DI0 Clock.*/
|
||||
ccmRootmuxM4ClkLdbDi1Clk = 5U, /*!< M4 clock from LDB DI1 Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for m4_pre_clk_sel. */
|
||||
enum _ccm_rootmux_m4_pre_clk_sel
|
||||
{
|
||||
ccmRootmuxM4PreClkPll2 = 0U, /*!< M4 pre clock from PLL2.*/
|
||||
ccmRootmuxM4PreClkPll3SwClk = 1U, /*!< M4 pre clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxM4PreClkOsc24m = 2U, /*!< M4 pre clock from OSC 24M.*/
|
||||
ccmRootmuxM4PreClkPll2Pfd0 = 3U, /*!< M4 pre clock from PLL2 PFD0.*/
|
||||
ccmRootmuxM4PreClkPll2Pfd2 = 4U, /*!< M4 pre clock from PLL2 PFD2.*/
|
||||
ccmRootmuxM4PreClkPll3Pfd3 = 5U, /*!< M4 pre clock from PLL3 PFD3.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for nent_clk_sel. */
|
||||
enum _ccm_rootmux_enet_clk_sel
|
||||
{
|
||||
ccmRootmuxEnetClkEnetPreClk = 0U, /*!< Ethernet clock from Ethernet Pre Clock.*/
|
||||
ccmRootmuxEnetClkIppDi0Clk = 1U, /*!< Ethernet clock from IPP DI0 Clock.*/
|
||||
ccmRootmuxEnetClkIppDi1Clk = 2U, /*!< Ethernet clock from IPP DI1 Clock.*/
|
||||
ccmRootmuxEnetClkLdbDi0Clk = 3U, /*!< Ethernet clock from LDB DI0 Clock.*/
|
||||
ccmRootmuxEnetClkLdbDi1Clk = 4U, /*!< Ethernet clock from LDB DI1 Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for enet_pre_clk_sel. */
|
||||
enum _ccm_rootmux_enet_pre_clk_sel
|
||||
{
|
||||
ccmRootmuxEnetPreClkPll2 = 0U, /*!< Ethernet Pre clock from PLL2.*/
|
||||
ccmRootmuxEnetPreClkPll3SwClk = 1U, /*!< Ethernet Pre clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxEnetPreClkPll5 = 2U, /*!< Ethernet Pre clock from PLL5.*/
|
||||
ccmRootmuxEnetPreClkPll2Pfd0 = 3U, /*!< Ethernet Pre clock from PLL2 PFD0.*/
|
||||
ccmRootmuxEnetPreClkPll2Pfd2 = 4U, /*!< Ethernet Pre clock from PLL2 PFD2.*/
|
||||
ccmRootmuxEnetPreClkPll3Pfd2 = 5U, /*!< Ethernet Pre clock from PLL3 PFD2.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for qspi2_clk_sel. */
|
||||
enum _ccm_rootmux_qspi2_clk_sel
|
||||
{
|
||||
ccmRootmuxQspi2ClkPll2Pfd0 = 0U, /*!< QSPI2 Clock from PLL2 PFD0.*/
|
||||
ccmRootmuxQspi2ClkPll2 = 1U, /*!< QSPI2 Clock from PLL2.*/
|
||||
ccmRootmuxQspi2ClkPll3SwClk = 2U, /*!< QSPI2 Clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxQspi2ClkPll2Pfd2 = 3U, /*!< QSPI2 Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxQspi2ClkPll3Pfd3 = 4U, /*!< QSPI2 Clock from PLL3 PFD3.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for display_clk_sel. */
|
||||
enum _ccm_rootmux_display_clk_sel
|
||||
{
|
||||
ccmRootmuxDisplayClkPll2 = 0U, /*!< Display Clock from PLL2.*/
|
||||
ccmRootmuxDisplayClkPll2Pfd2 = 1U, /*!< Display Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxDisplayClkPll3SwClk = 2U, /*!< Display Clock from PLL3 SW Clock.*/
|
||||
ccmRootmuxDisplayClkPll3Pfd1 = 3U, /*!< Display Clock from PLL3 PFD1.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for csi_clk_sel. */
|
||||
enum _ccm_rootmux_csi_clk_sel
|
||||
{
|
||||
ccmRootmuxCsiClkOSC24m = 0U, /*!< CSI Clock from OSC 24M.*/
|
||||
ccmRootmuxCsiClkPll2Pfd2 = 1U, /*!< CSI Clock from PLL2 PFD2.*/
|
||||
ccmRootmuxCsiClkPll3SwClkDiv2 = 2U, /*!< CSI Clock from PLL3 SW clock divided by 2.*/
|
||||
ccmRootmuxCsiClkPll3Pfd1 = 3U, /*!< CSI Clock from PLL3 PFD1.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for can_clk_sel. */
|
||||
enum _ccm_rootmux_can_clk_sel
|
||||
{
|
||||
ccmRootmuxCanClkPll3SwClkDiv8 = 0U, /*!< CAN Clock from PLL3 SW clock divided by 8.*/
|
||||
ccmRootmuxCanClkOsc24m = 1U, /*!< CAN Clock from OSC 24M.*/
|
||||
ccmRootmuxCanClkPll3SwClkDiv6 = 2U, /*!< CAN Clock from PLL3 SW clock divided by 6.*/
|
||||
ccmRootmuxCanClkDisableFlexcanClk = 3U, /*!< Disable FlexCAN clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for ecspi_clk_sel. */
|
||||
enum _ccm_rootmux_ecspi_clk_sel
|
||||
{
|
||||
ccmRootmuxEcspiClkPll3SwClkDiv8 = 0U, /*!< ecSPI Clock from PLL3 SW clock divided by 8.*/
|
||||
ccmRootmuxEcspiClkOsc24m = 1U, /*!< ecSPI Clock from OSC 24M.*/
|
||||
};
|
||||
|
||||
/*! @brief Root clock select enumeration for uart_clk_sel. */
|
||||
enum _ccm_rootmux_uart_clk_sel
|
||||
{
|
||||
ccmRootmuxUartClkPll3SwClkDiv6 = 0U, /*!< UART Clock from PLL3 SW clock divided by 6.*/
|
||||
ccmRootmuxUartClkOsc24m = 1U, /*!< UART Clock from OSC 24M.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief Root control names for root divider setting.
|
||||
*
|
||||
* These constants define the root control names for root divider setting.\n
|
||||
* - 0:7: REG offset to CCM_BASE in bytes.
|
||||
* - 8:15: Root divider setting bit field shift.
|
||||
* - 16:31: Root divider setting bit field width.
|
||||
*/
|
||||
enum _ccm_root_div_control
|
||||
{
|
||||
ccmRootArmPodf = CCM_TUPLE(CACRR, CCM_CACRR_arm_podf_SHIFT, CCM_CACRR_arm_podf_MASK), /*!< ARM Clock post divider control names.*/
|
||||
ccmRootFabricMmdcPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_fabric_mmdc_podf_SHIFT, CCM_CBCDR_fabric_mmdc_podf_MASK), /*!< Fabric MMDC Clock post divider control names.*/
|
||||
ccmRootPeriph2Clk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk2_podf_SHIFT, CCM_CBCDR_periph2_clk2_podf_MASK), /*!< Peripheral2 Clock2 post divider control names.*/
|
||||
ccmRootOcramPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_podf_SHIFT, CCM_CBCDR_ocram_podf_MASK), /*!< OCRAM Clock post divider control names.*/
|
||||
ccmRootAhbPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ahb_podf_SHIFT, CCM_CBCDR_ahb_podf_MASK), /*!< AHB Clock post divider control names.*/
|
||||
ccmRootPeriphClk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk2_podf_SHIFT, CCM_CBCDR_periph_clk2_podf_MASK), /*!< Peripheral Clock2 post divider control names.*/
|
||||
ccmRootPerclkPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_podf_SHIFT, CCM_CSCMR1_perclk_podf_MASK), /*!< Pre Clock post divider control names.*/
|
||||
ccmRootIpgPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ipg_podf_SHIFT, CCM_CBCDR_ipg_podf_MASK), /*!< IPG Clock post divider control names.*/
|
||||
ccmRootUsdhc1Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc1_podf_SHIFT, CCM_CSCDR1_usdhc1_podf_MASK), /*!< USDHC1 Clock post divider control names.*/
|
||||
ccmRootUsdhc2Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc2_podf_SHIFT, CCM_CSCDR1_usdhc2_podf_MASK), /*!< USDHC2 Clock post divider control names.*/
|
||||
ccmRootUsdhc3Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc3_podf_SHIFT, CCM_CSCDR1_usdhc3_podf_MASK), /*!< USDHC3 Clock post divider control names.*/
|
||||
ccmRootUsdhc4Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc4_podf_SHIFT, CCM_CSCDR1_usdhc4_podf_MASK), /*!< USDHC4 Clock post divider control names.*/
|
||||
ccmRootAclkEimSlowPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_podf_SHIFT, CCM_CSCMR1_aclk_eim_slow_podf_MASK), /*!< ACLK EIM SLOW Clock post divider control names.*/
|
||||
ccmRootGpuAxiPodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_podf_SHIFT, CCM_CBCMR_gpu_axi_podf_MASK), /*!< GPU AXI Clock post divider control names.*/
|
||||
ccmRootGpuCorePodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_podf_SHIFT, CCM_CBCMR_gpu_core_podf_MASK), /*!< GPU Core Clock post divider control names.*/
|
||||
ccmRootVidClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_podf_SHIFT, CCM_CSCMR2_vid_clk_podf_MASK), /*!< VID Clock post divider control names.*/
|
||||
ccmRootEsaiClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_podf_SHIFT, CCM_CS1CDR_esai_clk_podf_MASK), /*!< ESAI Clock pre divider control names.*/
|
||||
ccmRootEsaiClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_pred_SHIFT, CCM_CS1CDR_esai_clk_pred_MASK), /*!< ESAI Clock post divider control names.*/
|
||||
ccmRootAudioClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_podf_SHIFT, CCM_CDCDR_audio_clk_podf_MASK), /*!< AUDIO Clock post divider control names.*/
|
||||
ccmRootAudioClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_pred_SHIFT, CCM_CDCDR_audio_clk_pred_MASK), /*!< AUDIO Clock pre divider control names.*/
|
||||
ccmRootSpdif0ClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_podf_SHIFT, CCM_CDCDR_spdif0_clk_podf_MASK), /*!< SPDIF0 Clock post divider control names.*/
|
||||
ccmRootSpdif0ClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_pred_SHIFT, CCM_CDCDR_spdif0_clk_pred_MASK), /*!< SPDIF0 Clock pre divider control names.*/
|
||||
ccmRootSsi1ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_podf_SHIFT, CCM_CS1CDR_ssi1_clk_podf_MASK), /*!< SSI1 Clock post divider control names.*/
|
||||
ccmRootSsi1ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_pred_SHIFT, CCM_CS1CDR_ssi1_clk_pred_MASK), /*!< SSI1 Clock pre divider control names.*/
|
||||
ccmRootSsi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_podf_SHIFT, CCM_CS2CDR_ssi2_clk_podf_MASK), /*!< SSI2 Clock post divider control names.*/
|
||||
ccmRootSsi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_pred_SHIFT, CCM_CS2CDR_ssi2_clk_pred_MASK), /*!< SSI2 Clock pre divider control names.*/
|
||||
ccmRootSsi3ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_podf_SHIFT, CCM_CS1CDR_ssi3_clk_podf_MASK), /*!< SSI3 Clock post divider control names.*/
|
||||
ccmRootSsi3ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_pred_SHIFT, CCM_CS1CDR_ssi3_clk_pred_MASK), /*!< SSI3 Clock pre divider control names.*/
|
||||
ccmRootLcdif2Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_lcdif2_podf_SHIFT, CCM_CSCMR1_lcdif2_podf_MASK), /*!< LCDIF2 Clock post divider control names.*/
|
||||
ccmRootLcdif2Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pred_SHIFT, CCM_CSCDR2_lcdif2_pred_MASK), /*!< LCDIF2 Clock pre divider control names.*/
|
||||
ccmRootLdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di1_div_SHIFT, CCM_CSCMR2_ldb_di1_div_MASK), /*!< LDB DI1 Clock divider control names.*/
|
||||
ccmRootLdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di0_div_SHIFT, CCM_CSCMR2_ldb_di0_div_MASK), /*!< LCDIDI0 Clock divider control names.*/
|
||||
ccmRootLcdif1Podf = CCM_TUPLE(CBCMR, CCM_CBCMR_lcdif1_podf_SHIFT, CCM_CBCMR_lcdif1_podf_MASK), /*!< LCDIF1 Clock post divider control names.*/
|
||||
ccmRootLcdif1Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pred_SHIFT, CCM_CSCDR2_lcdif1_pred_MASK), /*!< LCDIF1 Clock pre divider control names.*/
|
||||
ccmRootM4Podf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_podf_SHIFT, CCM_CHSCCDR_m4_podf_MASK), /*!< M4 Clock post divider control names.*/
|
||||
ccmRootEnetPodf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_podf_SHIFT, CCM_CHSCCDR_enet_podf_MASK), /*!< Ethernet Clock post divider control names.*/
|
||||
ccmRootQspi1Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_qspi1_podf_SHIFT, CCM_CSCMR1_qspi1_podf_MASK), /*!< QSPI1 Clock post divider control names.*/
|
||||
ccmRootQspi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_podf_SHIFT, CCM_CS2CDR_qspi2_clk_podf_MASK), /*!< QSPI2 Clock post divider control names.*/
|
||||
ccmRootQspi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_pred_SHIFT, CCM_CS2CDR_qspi2_clk_pred_MASK), /*!< QSPI2 Clock pre divider control names.*/
|
||||
ccmRootDisplayPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_podf_SHIFT, CCM_CSCDR3_display_podf_MASK), /*!< Display Clock post divider control names.*/
|
||||
ccmRootCsiPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_podf_SHIFT, CCM_CSCDR3_csi_podf_MASK), /*!< CSI Clock post divider control names.*/
|
||||
ccmRootCanClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_podf_SHIFT, CCM_CSCMR2_can_clk_podf_MASK), /*!< CAN Clock post divider control names.*/
|
||||
ccmRootEcspiClkPodf = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_podf_SHIFT, CCM_CSCDR2_ecspi_clk_podf_MASK), /*!< ECSPI Clock post divider control names.*/
|
||||
ccmRootUartClkPodf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_podf_SHIFT, CCM_CSCDR1_uart_clk_podf_MASK) /*!< UART Clock post divider control names.*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief CCM CCGR gate control for each module independently.
|
||||
*
|
||||
* These constants define the ccm ccgr clock gate for each module.\n
|
||||
* - 0:7: REG offset to CCM_BASE in bytes.
|
||||
* - 8:15: Root divider setting bit field shift.
|
||||
* - 16:31: Root divider setting bit field width.
|
||||
*/
|
||||
enum _ccm_ccgr_gate
|
||||
{
|
||||
ccmCcgrGateAipsTz1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG0_SHIFT, CCM_CCGR0_CG0_MASK), /*!< AipsTz1 Clock Gate.*/
|
||||
ccmCcgrGateAipsTz2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG1_SHIFT, CCM_CCGR0_CG1_MASK), /*!< AipsTz2 Clock Gate.*/
|
||||
ccmCcgrGateApbhdmaHclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG2_SHIFT, CCM_CCGR0_CG2_MASK), /*!< ApbhdmaH Clock Gate.*/
|
||||
ccmCcgrGateAsrcClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG3_SHIFT, CCM_CCGR0_CG3_MASK), /*!< Asrc Clock Gate.*/
|
||||
ccmCcgrGateCaamSecureMemClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG4_SHIFT, CCM_CCGR0_CG4_MASK), /*!< CaamSecureMem Clock Gate.*/
|
||||
ccmCcgrGateCaamWrapperAclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG5_SHIFT, CCM_CCGR0_CG5_MASK), /*!< CaamWrapperA Clock Gate.*/
|
||||
ccmCcgrGateCaamWrapperIpg = CCM_TUPLE(CCGR0, CCM_CCGR0_CG6_SHIFT, CCM_CCGR0_CG6_MASK), /*!< CaamWrapperIpg Clock Gate.*/
|
||||
ccmCcgrGateCan1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG7_SHIFT, CCM_CCGR0_CG7_MASK), /*!< Can1 Clock Gate.*/
|
||||
ccmCcgrGateCan1SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG8_SHIFT, CCM_CCGR0_CG8_MASK), /*!< Can1 Serial Clock Gate.*/
|
||||
ccmCcgrGateCan2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG9_SHIFT, CCM_CCGR0_CG9_MASK), /*!< Can2 Clock Gate.*/
|
||||
ccmCcgrGateCan2SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG10_SHIFT, CCM_CCGR0_CG10_MASK), /*!< Can2 Serial Clock Gate.*/
|
||||
ccmCcgrGateArmDbgClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG11_SHIFT, CCM_CCGR0_CG11_MASK), /*!< Arm Debug Clock Gate.*/
|
||||
ccmCcgrGateDcic1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG12_SHIFT, CCM_CCGR0_CG12_MASK), /*!< Dcic1 Clock Gate.*/
|
||||
ccmCcgrGateDcic2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG13_SHIFT, CCM_CCGR0_CG13_MASK), /*!< Dcic2 Clock Gate.*/
|
||||
ccmCcgrGateAipsTz3Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG15_SHIFT, CCM_CCGR0_CG15_MASK), /*!< AipsTz3 Clock Gate.*/
|
||||
ccmCcgrGateEcspi1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG0_SHIFT, CCM_CCGR1_CG0_MASK), /*!< Ecspi1 Clock Gate.*/
|
||||
ccmCcgrGateEcspi2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG1_SHIFT, CCM_CCGR1_CG1_MASK), /*!< Ecspi2 Clock Gate.*/
|
||||
ccmCcgrGateEcspi3Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG2_SHIFT, CCM_CCGR1_CG2_MASK), /*!< Ecspi3 Clock Gate.*/
|
||||
ccmCcgrGateEcspi4Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG3_SHIFT, CCM_CCGR1_CG3_MASK), /*!< Ecspi4 Clock Gate.*/
|
||||
ccmCcgrGateEcspi5Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG4_SHIFT, CCM_CCGR1_CG4_MASK), /*!< Ecspi5 Clock Gate.*/
|
||||
ccmCcgrGateEpit1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG6_SHIFT, CCM_CCGR1_CG6_MASK), /*!< Epit1 Clock Gate.*/
|
||||
ccmCcgrGateEpit2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG7_SHIFT, CCM_CCGR1_CG7_MASK), /*!< Epit2 Clock Gate.*/
|
||||
ccmCcgrGateEsaiClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG8_SHIFT, CCM_CCGR1_CG8_MASK), /*!< Esai Clock Gate.*/
|
||||
ccmCcgrGateWakeupClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG9_SHIFT, CCM_CCGR1_CG9_MASK), /*!< Wakeup Clock Gate.*/
|
||||
ccmCcgrGateGptClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG10_SHIFT, CCM_CCGR1_CG10_MASK), /*!< Gpt Clock Gate.*/
|
||||
ccmCcgrGateGptSerialClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG11_SHIFT, CCM_CCGR1_CG11_MASK), /*!< Gpt Serial Clock Gate.*/
|
||||
ccmCcgrGateGpuClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG13_SHIFT, CCM_CCGR1_CG13_MASK), /*!< Gpu Clock Gate.*/
|
||||
ccmCcgrGateOcramSClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG14_SHIFT, CCM_CCGR1_CG14_MASK), /*!< OcramS Clock Gate.*/
|
||||
ccmCcgrGateCanfdClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG15_SHIFT, CCM_CCGR1_CG15_MASK), /*!< Canfd Clock Gate.*/
|
||||
ccmCcgrGateCsiClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG1_SHIFT, CCM_CCGR2_CG1_MASK), /*!< Csi Clock Gate.*/
|
||||
ccmCcgrGateI2c1Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG3_SHIFT, CCM_CCGR2_CG3_MASK), /*!< I2c1 Serial Clock Gate.*/
|
||||
ccmCcgrGateI2c2Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG4_SHIFT, CCM_CCGR2_CG4_MASK), /*!< I2c2 Serial Clock Gate.*/
|
||||
ccmCcgrGateI2c3Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG5_SHIFT, CCM_CCGR2_CG5_MASK), /*!< I2c3 Serial Clock Gate.*/
|
||||
ccmCcgrGateIimClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG6_SHIFT, CCM_CCGR2_CG6_MASK), /*!< Iim Clock Gate.*/
|
||||
ccmCcgrGateIomuxIptClkIo = CCM_TUPLE(CCGR2, CCM_CCGR2_CG7_SHIFT, CCM_CCGR2_CG7_MASK), /*!< Iomux Ipt Clock Gate.*/
|
||||
ccmCcgrGateIpmux1Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG8_SHIFT, CCM_CCGR2_CG8_MASK), /*!< Ipmux1 Clock Gate.*/
|
||||
ccmCcgrGateIpmux2Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG9_SHIFT, CCM_CCGR2_CG9_MASK), /*!< Ipmux2 Clock Gate.*/
|
||||
ccmCcgrGateIpmux3Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG10_SHIFT, CCM_CCGR2_CG10_MASK), /*!< Ipmux3 Clock Gate.*/
|
||||
ccmCcgrGateIpsyncIp2apbtTasc1 = CCM_TUPLE(CCGR2, CCM_CCGR2_CG11_SHIFT, CCM_CCGR2_CG11_MASK), /*!< IpsyncIp2apbtTasc1 Clock Gate.*/
|
||||
ccmCcgrGateLcdClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG14_SHIFT, CCM_CCGR2_CG14_MASK), /*!< Lcd Clock Gate.*/
|
||||
ccmCcgrGatePxpClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG15_SHIFT, CCM_CCGR2_CG15_MASK), /*!< Pxp Clock Gate.*/
|
||||
ccmCcgrGateM4Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG1_SHIFT, CCM_CCGR3_CG1_MASK), /*!< M4 Clock Gate.*/
|
||||
ccmCcgrGateEnetClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG2_SHIFT, CCM_CCGR3_CG2_MASK), /*!< Enet Clock Gate.*/
|
||||
ccmCcgrGateDispAxiClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG3_SHIFT, CCM_CCGR3_CG3_MASK), /*!< DispAxi Clock Gate.*/
|
||||
ccmCcgrGateLcdif2PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG4_SHIFT, CCM_CCGR3_CG4_MASK), /*!< Lcdif2Pix Clock Gate.*/
|
||||
ccmCcgrGateLcdif1PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG5_SHIFT, CCM_CCGR3_CG5_MASK), /*!< Lcdif1Pix Clock Gate.*/
|
||||
ccmCcgrGateLdbDi0Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG6_SHIFT, CCM_CCGR3_CG6_MASK), /*!< LdbDi0 Clock Gate.*/
|
||||
ccmCcgrGateQspi1Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG7_SHIFT, CCM_CCGR3_CG7_MASK), /*!< Qspi1 Clock Gate.*/
|
||||
ccmCcgrGateMlbClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG9_SHIFT, CCM_CCGR3_CG9_MASK), /*!< Mlb Clock Gate.*/
|
||||
ccmCcgrGateMmdcCoreAclkFastP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG10_SHIFT, CCM_CCGR3_CG10_MASK), /*!< Mmdc Core Aclk FastP0 Clock Gate.*/
|
||||
ccmCcgrGateMmdcCoreIpgClkP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG12_SHIFT, CCM_CCGR3_CG12_MASK), /*!< Mmdc Core Ipg Clk P0 Clock Gate.*/
|
||||
ccmCcgrGateMmdcCoreIpgClkP1 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG13_SHIFT, CCM_CCGR3_CG13_MASK), /*!< Mmdc Core Ipg Clk P1 Clock Gate.*/
|
||||
ccmCcgrGateOcramClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG14_SHIFT, CCM_CCGR3_CG14_MASK), /*!< Ocram Clock Gate.*/
|
||||
ccmCcgrGatePcieRoot = CCM_TUPLE(CCGR4, CCM_CCGR4_CG0_SHIFT, CCM_CCGR4_CG0_MASK), /*!< Pcie Clock Gate.*/
|
||||
ccmCcgrGateQspi2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG5_SHIFT, CCM_CCGR4_CG5_MASK), /*!< Qspi2 Clock Gate.*/
|
||||
ccmCcgrGatePl301Mx6qper1Bch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG6_SHIFT, CCM_CCGR4_CG6_MASK), /*!< Pl301Mx6qper1Bch Clock Gate.*/
|
||||
ccmCcgrGatePl301Mx6qper2Main = CCM_TUPLE(CCGR4, CCM_CCGR4_CG7_SHIFT, CCM_CCGR4_CG7_MASK), /*!< Pl301Mx6qper2Main Clock Gate.*/
|
||||
ccmCcgrGatePwm1Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG8_SHIFT, CCM_CCGR4_CG8_MASK), /*!< Pwm1 Clock Gate.*/
|
||||
ccmCcgrGatePwm2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG9_SHIFT, CCM_CCGR4_CG9_MASK), /*!< Pwm2 Clock Gate.*/
|
||||
ccmCcgrGatePwm3Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG10_SHIFT, CCM_CCGR4_CG10_MASK), /*!< Pwm3 Clock Gate.*/
|
||||
ccmCcgrGatePwm4Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG11_SHIFT, CCM_CCGR4_CG11_MASK), /*!< Pwm4 Clock Gate.*/
|
||||
ccmCcgrGateRawnandUBchInptApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG12_SHIFT, CCM_CCGR4_CG12_MASK), /*!< RawnandUBchInptApb Clock Gate.*/
|
||||
ccmCcgrGateRawnandUGpmiBch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG13_SHIFT, CCM_CCGR4_CG13_MASK), /*!< RawnandUGpmiBch Clock Gate.*/
|
||||
ccmCcgrGateRawnandUGpmiGpmiIo = CCM_TUPLE(CCGR4, CCM_CCGR4_CG14_SHIFT, CCM_CCGR4_CG14_MASK), /*!< RawnandUGpmiGpmiIo Clock Gate.*/
|
||||
ccmCcgrGateRawnandUGpmiInpApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG15_SHIFT, CCM_CCGR4_CG15_MASK), /*!< RawnandUGpmiInpApb Clock Gate.*/
|
||||
ccmCcgrGateRomClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG0_SHIFT, CCM_CCGR5_CG0_MASK), /*!< Rom Clock Gate.*/
|
||||
ccmCcgrGateSdmaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG3_SHIFT, CCM_CCGR5_CG3_MASK), /*!< Sdma Clock Gate.*/
|
||||
ccmCcgrGateSpbaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG6_SHIFT, CCM_CCGR5_CG6_MASK), /*!< Spba Clock Gate.*/
|
||||
ccmCcgrGateSpdifAudioClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG7_SHIFT, CCM_CCGR5_CG7_MASK), /*!< SpdifAudio Clock Gate.*/
|
||||
ccmCcgrGateSsi1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG9_SHIFT, CCM_CCGR5_CG9_MASK), /*!< Ssi1 Clock Gate.*/
|
||||
ccmCcgrGateSsi2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG10_SHIFT, CCM_CCGR5_CG10_MASK), /*!< Ssi2 Clock Gate.*/
|
||||
ccmCcgrGateSsi3Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG11_SHIFT, CCM_CCGR5_CG11_MASK), /*!< Ssi3 Clock Gate.*/
|
||||
ccmCcgrGateUartClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG12_SHIFT, CCM_CCGR5_CG12_MASK), /*!< Uart Clock Gate.*/
|
||||
ccmCcgrGateUartSerialClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG13_SHIFT, CCM_CCGR5_CG13_MASK), /*!< Uart Serial Clock Gate.*/
|
||||
ccmCcgrGateSai1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG14_SHIFT, CCM_CCGR5_CG14_MASK), /*!< Sai1 Clock Gate.*/
|
||||
ccmCcgrGateSai2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG15_SHIFT, CCM_CCGR5_CG15_MASK), /*!< Sai2 Clock Gate.*/
|
||||
ccmCcgrGateUsboh3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG0_SHIFT, CCM_CCGR6_CG0_MASK), /*!< Usboh3 Clock Gate.*/
|
||||
ccmCcgrGateUsdhc1Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG1_SHIFT, CCM_CCGR6_CG1_MASK), /*!< Usdhc1 Clock Gate.*/
|
||||
ccmCcgrGateUsdhc2Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG2_SHIFT, CCM_CCGR6_CG2_MASK), /*!< Usdhc2 Clock Gate.*/
|
||||
ccmCcgrGateUsdhc3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG3_SHIFT, CCM_CCGR6_CG3_MASK), /*!< Usdhc3 Clock Gate.*/
|
||||
ccmCcgrGateUsdhc4Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG4_SHIFT, CCM_CCGR6_CG4_MASK), /*!< Usdhc4 Clock Gate.*/
|
||||
ccmCcgrGateEimSlowClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG5_SHIFT, CCM_CCGR6_CG5_MASK), /*!< EimSlow Clock Gate.*/
|
||||
ccmCcgrGatePwm8Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG8_SHIFT, CCM_CCGR6_CG8_MASK), /*!< Pwm8 Clock Gate.*/
|
||||
ccmCcgrGateVadcClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG10_SHIFT, CCM_CCGR6_CG10_MASK), /*!< Vadc Clock Gate.*/
|
||||
ccmCcgrGateGisClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG11_SHIFT, CCM_CCGR6_CG11_MASK), /*!< Gis Clock Gate.*/
|
||||
ccmCcgrGateI2c4SerialClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG12_SHIFT, CCM_CCGR6_CG12_MASK), /*!< I2c4 Serial Clock Gate.*/
|
||||
ccmCcgrGatePwm5Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG13_SHIFT, CCM_CCGR6_CG13_MASK), /*!< Pwm5 Clock Gate.*/
|
||||
ccmCcgrGatePwm6Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG14_SHIFT, CCM_CCGR6_CG14_MASK), /*!< Pwm6 Clock Gate.*/
|
||||
ccmCcgrGatePwm7Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG15_SHIFT, CCM_CCGR6_CG15_MASK), /*!< Pwm7 Clock Gate.*/
|
||||
};
|
||||
|
||||
/*! @brief CCM gate control value. */
|
||||
enum _ccm_gate_value
|
||||
{
|
||||
ccmClockNotNeeded = 0U, /*!< Clock always disabled.*/
|
||||
ccmClockNeededRun = 1U, /*!< Clock enabled when CPU is running.*/
|
||||
ccmClockNeededAll = 3U /*!< Clock always enabled.*/
|
||||
};
|
||||
|
||||
/*! @brief CCM override clock enable signal from module. */
|
||||
enum _ccm_overrided_enable_signal
|
||||
{
|
||||
ccmOverridedSignalFromGpt = 1U << 5, /*!< Override clock enable signal from GPT.*/
|
||||
ccmOverridedSignalFromEpit = 1U << 6, /*!< Override clock enable signal from EPIT.*/
|
||||
ccmOverridedSignalFromUsdhc = 1U << 7, /*!< Override clock enable signal from USDHC.*/
|
||||
ccmOverridedSignalFromGpu = 1U << 10, /*!< Override clock enable signal from GPU.*/
|
||||
ccmOverridedSignalFromCan2Cpi = 1U << 28, /*!< Override clock enable signal from CAN2.*/
|
||||
ccmOverridedSignalFromCan1Cpi = 1U << 30 /*!< Override clock enable signal from CAN1.*/
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name CCM Root Clock Setting
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set clock root mux.
|
||||
* User maybe need to set more than one mux node according to the clock tree
|
||||
* description on the reference manual.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration).
|
||||
* @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration).
|
||||
*/
|
||||
static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRootClk, uint32_t mux)
|
||||
{
|
||||
CCM_TUPLE_REG(base, ccmRootClk) = (CCM_TUPLE_REG(base, ccmRootClk) & (~CCM_TUPLE_MASK(ccmRootClk))) |
|
||||
(((uint32_t)((mux) << CCM_TUPLE_SHIFT(ccmRootClk))) & CCM_TUPLE_MASK(ccmRootClk));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get clock root mux.
|
||||
* In order to get the clock source of root, user maybe need to get more than one
|
||||
* node's mux value to obtain the final clock source of root.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration).
|
||||
* @return Root mux value (see @ref _ccm_rootmux_xxx enumeration).
|
||||
*/
|
||||
static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRootClk)
|
||||
{
|
||||
return (CCM_TUPLE_REG(base, ccmRootClk) & CCM_TUPLE_MASK(ccmRootClk)) >> CCM_TUPLE_SHIFT(ccmRootClk);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set root clock divider.
|
||||
* User should set the dividers carefully according to the clock tree on
|
||||
* the reference manual. Take care of that the setting of one divider value
|
||||
* may affect several clock root.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param ccmRootDiv Root divider control (see @ref _ccm_root_div_control enumeration)
|
||||
* @param div Divider value (divider = div + 1).
|
||||
*/
|
||||
static inline void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRootDiv, uint32_t div)
|
||||
{
|
||||
CCM_TUPLE_REG(base, ccmRootDiv) = (CCM_TUPLE_REG(base, ccmRootDiv) & (~CCM_TUPLE_MASK(ccmRootDiv))) |
|
||||
(((uint32_t)((div) << CCM_TUPLE_SHIFT(ccmRootDiv))) & CCM_TUPLE_MASK(ccmRootDiv));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get root clock divider.
|
||||
* In order to get divider value of clock root, user should get specific
|
||||
* divider value according to the clock tree description on reference manual.
|
||||
* Then calculate the root clock with those divider value.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param ccmRootDiv Root control (see @ref _ccm_root_div_control enumeration).
|
||||
* @param div Pointer to divider value store address.
|
||||
* @return Root divider value.
|
||||
*/
|
||||
static inline uint32_t CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRootDiv)
|
||||
{
|
||||
return (CCM_TUPLE_REG(base, ccmRootDiv) & CCM_TUPLE_MASK(ccmRootDiv)) >> CCM_TUPLE_SHIFT(ccmRootDiv);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set handshake mask of MMDC module.
|
||||
* During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel
|
||||
* change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param mask True: mask handshake with MMDC; False: allow handshake with MMDC.
|
||||
*/
|
||||
void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name CCM Gate Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set CCGR gate control for each module
|
||||
* User should set specific gate for each module according to the description
|
||||
* of the table of system clocks, gating and override in CCM chapter of
|
||||
* reference manual. Take care of that one module may need to set more than
|
||||
* one clock gate.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param ccmGate Gate control for each module (see @ref _ccm_ccgr_gate enumeration).
|
||||
* @param control Gate control value (see @ref _ccm_gate_value).
|
||||
*/
|
||||
static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control)
|
||||
{
|
||||
CCM_TUPLE_REG(base, ccmGate) = (CCM_TUPLE_REG(base, ccmGate) & (~CCM_TUPLE_MASK(ccmGate))) |
|
||||
(((uint32_t)((control) << CCM_TUPLE_SHIFT(ccmGate))) & CCM_TUPLE_MASK(ccmGate));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set override or do not override clock enable signal from module.
|
||||
* This is applicable only for modules whose clock enable signals are used.
|
||||
*
|
||||
* @param base CCM base pointer.
|
||||
* @param signal Overrided enable signal from module (see @ref _ccm_overrided_enable_signal enumeration).
|
||||
* @param control Override / Do not override clock enable signal from module.
|
||||
* - true: override clock enable signal.
|
||||
* - false: Do not override clock enable signal.
|
||||
*/
|
||||
void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __CCM_IMX6SX_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
89
ext/hal/nxp/imx/drivers/epit.c
Executable file
89
ext/hal/nxp/imx/drivers/epit.c
Executable file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "epit.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : EPIT_Init
|
||||
* Description : Initializes the EPIT module according to the specified
|
||||
* parameters in the initConfig.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig)
|
||||
{
|
||||
assert(initConfig);
|
||||
|
||||
EPIT_CR_REG(base) = 0;
|
||||
|
||||
EPIT_SoftReset(base);
|
||||
|
||||
EPIT_CR_REG(base) = (initConfig->freeRun ? EPIT_CR_RLD_MASK : 0) |
|
||||
(initConfig->waitEnable ? EPIT_CR_WAITEN_MASK : 0) |
|
||||
(initConfig->stopEnable ? EPIT_CR_STOPEN_MASK : 0) |
|
||||
(initConfig->dbgEnable ? EPIT_CR_DBGEN_MASK : 0) |
|
||||
(initConfig->enableMode ? EPIT_CR_ENMOD_MASK : 0);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : EPIT_SetOverwriteCounter
|
||||
* Description : Enable or disable EPIT overwrite counter immediately.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable)
|
||||
{
|
||||
if(enable)
|
||||
EPIT_CR_REG(base) |= EPIT_CR_IOVW_MASK;
|
||||
else
|
||||
EPIT_CR_REG(base) &= ~EPIT_CR_IOVW_MASK;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : EPIT_SetIntCmd
|
||||
* Description : Enable or disable EPIT interrupt.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void EPIT_SetIntCmd(EPIT_Type* base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
EPIT_CR_REG(base) |= EPIT_CR_OCIEN_MASK;
|
||||
else
|
||||
EPIT_CR_REG(base) &= ~EPIT_CR_OCIEN_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
326
ext/hal/nxp/imx/drivers/epit.h
Executable file
326
ext/hal/nxp/imx/drivers/epit.h
Executable file
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __EPIT_H__
|
||||
#define __EPIT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "device_imx.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup epit_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Clock source. */
|
||||
enum _epit_clock_source
|
||||
{
|
||||
epitClockSourceOff = 0U, /*!< EPIT Clock Source Off.*/
|
||||
epitClockSourcePeriph = 1U, /*!< EPIT Clock Source from Peripheral Clock.*/
|
||||
epitClockSourceHighFreq = 2U, /*!< EPIT Clock Source from High Frequency Reference Clock.*/
|
||||
epitClockSourceLowFreq = 3U, /*!< EPIT Clock Source from Low Frequency Reference Clock.*/
|
||||
};
|
||||
|
||||
/*! @brief Output compare operation mode. */
|
||||
enum _epit_output_operation_mode
|
||||
{
|
||||
epitOutputOperationDisconnected = 0U, /*!< EPIT Output Operation: Disconnected from pad.*/
|
||||
epitOutputOperationToggle = 1U, /*!< EPIT Output Operation: Toggle output pin.*/
|
||||
epitOutputOperationClear = 2U, /*!< EPIT Output Operation: Clear output pin.*/
|
||||
epitOutputOperationSet = 3U, /*!< EPIT Output Operation: Set putput pin.*/
|
||||
};
|
||||
|
||||
/*! @brief Structure to configure the running mode. */
|
||||
typedef struct _epit_init_config
|
||||
{
|
||||
bool freeRun; /*!< true: set-and-forget mode, false: free-running mode. */
|
||||
bool waitEnable; /*!< EPIT enabled in wait mode. */
|
||||
bool stopEnable; /*!< EPIT enabled in stop mode. */
|
||||
bool dbgEnable; /*!< EPIT enabled in debug mode. */
|
||||
bool enableMode; /*!< true: counter starts counting from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) when enabled,
|
||||
false: counter restores the value that it was disabled when enabled. */
|
||||
} epit_init_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name EPIT State Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize EPIT to reset state and initialize running mode.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param initConfig EPIT initialize structure.
|
||||
*/
|
||||
void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig);
|
||||
|
||||
/*!
|
||||
* @brief Software reset of EPIT module.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
*/
|
||||
static inline void EPIT_SoftReset(EPIT_Type* base)
|
||||
{
|
||||
EPIT_CR_REG(base) |= EPIT_CR_SWR_MASK;
|
||||
/* Wait reset finished. */
|
||||
while (EPIT_CR_REG(base) & EPIT_CR_SWR_MASK) { }
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set clock source of EPIT.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param source clock source (see @ref _epit_clock_source enumeration).
|
||||
*/
|
||||
static inline void EPIT_SetClockSource(EPIT_Type* base, uint32_t source)
|
||||
{
|
||||
EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get clock source of EPIT.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return clock source (see @ref _epit_clock_source enumeration).
|
||||
*/
|
||||
static inline uint32_t EPIT_GetClockSource(EPIT_Type* base)
|
||||
{
|
||||
return (EPIT_CR_REG(base) & EPIT_CR_CLKSRC_MASK) >> EPIT_CR_CLKSRC_SHIFT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set pre scaler of EPIT.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param prescaler Pre-scaler of EPIT (0-4095, divider = prescaler + 1).
|
||||
*/
|
||||
static inline void EPIT_SetPrescaler(EPIT_Type* base, uint32_t prescaler)
|
||||
{
|
||||
assert(prescaler <= (EPIT_CR_PRESCALAR_MASK >> EPIT_CR_PRESCALAR_SHIFT));
|
||||
EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_PRESCALAR_MASK) | EPIT_CR_PRESCALAR(prescaler);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get pre scaler of EPIT.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return Pre-scaler of EPIT (0-4095).
|
||||
*/
|
||||
static inline uint32_t EPIT_GetPrescaler(EPIT_Type* base)
|
||||
{
|
||||
return (EPIT_CR_REG(base) & EPIT_CR_PRESCALAR_MASK) >> EPIT_CR_PRESCALAR_SHIFT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable EPIT module.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
*/
|
||||
static inline void EPIT_Enable(EPIT_Type* base)
|
||||
{
|
||||
EPIT_CR_REG(base) |= EPIT_CR_EN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable EPIT module.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
*/
|
||||
static inline void EPIT_Disable(EPIT_Type* base)
|
||||
{
|
||||
EPIT_CR_REG(base) &= ~EPIT_CR_EN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get EPIT counter value.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return EPIT counter value.
|
||||
*/
|
||||
static inline uint32_t EPIT_ReadCounter(EPIT_Type* base)
|
||||
{
|
||||
return EPIT_CNR_REG(base);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name EPIT Output Signal Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set EPIT output compare operation mode.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param mode EPIT output compare operation mode (see @ref _epit_output_operation_mode enumeration).
|
||||
*/
|
||||
static inline void EPIT_SetOutputOperationMode(EPIT_Type* base, uint32_t mode)
|
||||
{
|
||||
EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_OM_MASK) | EPIT_CR_OM(mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get EPIT output compare operation mode.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return EPIT output operation mode (see @ref _epit_output_operation_mode enumeration).
|
||||
*/
|
||||
static inline uint32_t EPIT_GetOutputOperationMode(EPIT_Type* base)
|
||||
{
|
||||
return (EPIT_CR_REG(base) & EPIT_CR_OM_MASK) >> EPIT_CR_OM_SHIFT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set EPIT output compare value.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param value EPIT output compare value.
|
||||
*/
|
||||
static inline void EPIT_SetOutputCompareValue(EPIT_Type* base, uint32_t value)
|
||||
{
|
||||
EPIT_CMPR_REG(base) = value;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get EPIT output compare value.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return EPIT output compare value.
|
||||
*/
|
||||
static inline uint32_t EPIT_GetOutputCompareValue(EPIT_Type* base)
|
||||
{
|
||||
return EPIT_CMPR_REG(base);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name EPIT Data Load Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set the value that is to be loaded into counter register.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param value Counter load value.
|
||||
*/
|
||||
static inline void EPIT_SetCounterLoadValue(EPIT_Type* base, uint32_t value)
|
||||
{
|
||||
EPIT_LR_REG(base) = value;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the value that loaded into counter register.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return The counter load value.
|
||||
*/
|
||||
static inline uint32_t EPIT_GetCounterLoadValue(EPIT_Type* base)
|
||||
{
|
||||
return EPIT_LR_REG(base);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable or disable EPIT overwrite counter immediately.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param enable Enable/Disable EPIT overwrite counter immediately.
|
||||
* - true: Enable overwrite counter immediately.
|
||||
* - false: Disable overwrite counter immediately.
|
||||
*/
|
||||
void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name EPIT Interrupt and Status Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get EPIT status of output compare interrupt flag.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @return EPIT status of output compare interrupt flag.
|
||||
*/
|
||||
static inline uint32_t EPIT_GetStatusFlag(EPIT_Type* base)
|
||||
{
|
||||
return EPIT_SR_REG(base) & EPIT_SR_OCIF_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear EPIT Output compare interrupt flag.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
*/
|
||||
static inline void EPIT_ClearStatusFlag(EPIT_Type* base)
|
||||
{
|
||||
EPIT_SR_REG(base) = EPIT_SR_OCIF_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable or disable EPIT interrupt.
|
||||
*
|
||||
* @param base EPIT base pointer.
|
||||
* @param enable Enable/Disable EPIT interrupt.
|
||||
* - true: Enable interrupt.
|
||||
* - false: Disable interrupt.
|
||||
*/
|
||||
void EPIT_SetIntCmd(EPIT_Type* base, bool enable);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /*__EPIT_H__*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
210
ext/hal/nxp/imx/drivers/rdc_defs_imx6sx.h
Executable file
210
ext/hal/nxp/imx/drivers/rdc_defs_imx6sx.h
Executable file
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __RDC_DEFS_IMX6SX__
|
||||
#define __RDC_DEFS_IMX6SX__
|
||||
|
||||
/*!
|
||||
* @addtogroup rdc_def_imx6sx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief RDC master assignment. */
|
||||
enum _rdc_mda
|
||||
{
|
||||
rdcMdaA9L2Cache = 0U, /*!< A9 L2 Cache RDC Master. */
|
||||
rdcMdaM4 = 1U, /*!< M4 RDC Master. */
|
||||
rdcMdaGpu = 2U, /*!< GPU RDC Master. */
|
||||
rdcMdaCsi1 = 3U, /*!< Csi1 RDC Master. */
|
||||
rdcMdaCsi2 = 4U, /*!< Csi2 RDC Master. */
|
||||
rdcMdaLcdif1 = 5U, /*!< Lcdif1 RDC Master. */
|
||||
rdcMdaLcdif2 = 6U, /*!< Lcdif2 RDC Master. */
|
||||
rdcMdaPxp = 7U, /*!< Pxp RDC Master. */
|
||||
rdcMdaPcieCtrl = 8U, /*!< Pcie Ctrl RDC Master. */
|
||||
rdcMdaDap = 9U, /*!< Dap RDC Master. */
|
||||
rdcMdaCaam = 10U, /*!< Caam RDC Master. */
|
||||
rdcMdaSdmaPeriph = 11U, /*!< Sdma Periph RDC Master. */
|
||||
rdcMdaSdmaBurst = 12U, /*!< Sdma Burst RDC Master. */
|
||||
rdcMdaApbhdma = 13U, /*!< Apbhdma RDC Master. */
|
||||
rdcMdaRawnand = 14U, /*!< Rawnand RDC Master. */
|
||||
rdcMdaUsdhc1 = 15U, /*!< Usdhc1 RDC Master. */
|
||||
rdcMdaUsdhc2 = 16U, /*!< Usdhc2 RDC Master. */
|
||||
rdcMdaUsdhc3 = 17U, /*!< Usdhc3 RDC Master. */
|
||||
rdcMdaUsdhc4 = 18U, /*!< Usdhc4 RDC Master. */
|
||||
rdcMdaUsb = 19U, /*!< USB RDC Master. */
|
||||
rdcMdaMlb = 20U, /*!< MLB RDC Master. */
|
||||
rdcMdaTestPort = 21U, /*!< Test Port RDC Master. */
|
||||
rdcMdaEnet1Tx = 22U, /*!< Enet1 Tx RDC Master. */
|
||||
rdcMdaEnet1Rx = 23U, /*!< Enet1 Rx Master. */
|
||||
rdcMdaEnet2Tx = 24U, /*!< Enet2 Tx RDC Master. */
|
||||
rdcMdaEnet2Rx = 25U, /*!< Enet2 Rx RDC Master. */
|
||||
rdcMdaSdmaPort = 26U, /*!< Sdma Port RDC Master. */
|
||||
};
|
||||
|
||||
/*! @brief RDC peripheral assignment. */
|
||||
enum _rdc_pdap
|
||||
{
|
||||
rdcPdapPwm1 = 0U, /*!< Pwm1 RDC Peripheral. */
|
||||
rdcPdapPwm2 = 1U, /*!< Pwm2 RDC Peripheral. */
|
||||
rdcPdapPwm3 = 2U, /*!< Pwm3 RDC Peripheral. */
|
||||
rdcPdapPwm4 = 3U, /*!< Pwm4 RDC Peripheral. */
|
||||
rdcPdapCan1 = 4U, /*!< Can1 RDC Peripheral. */
|
||||
rdcPdapCan2 = 5U, /*!< Can2 RDC Peripheral. */
|
||||
rdcPdapGpt = 6U, /*!< Gpt RDC Peripheral. */
|
||||
rdcPdapGpio1 = 7U, /*!< Gpio1 RDC Peripheral. */
|
||||
rdcPdapGpio2 = 8U, /*!< Gpio2 RDC Peripheral. */
|
||||
rdcPdapGpio3 = 9U, /*!< Gpio3 RDC Peripheral. */
|
||||
rdcPdapGpio4 = 10U, /*!< Gpio4 RDC Peripheral. */
|
||||
rdcPdapGpio5 = 11U, /*!< Gpio5 RDC Peripheral. */
|
||||
rdcPdapGpio6 = 12U, /*!< Gpio6 RDC Peripheral. */
|
||||
rdcPdapGpio7 = 13U, /*!< Gpio7 RDC Peripheral. */
|
||||
rdcPdapKpp = 14U, /*!< Kpp RDC Peripheral. */
|
||||
rdcPdapWdog1 = 15U, /*!< Wdog1 RDC Peripheral. */
|
||||
rdcPdapWdog2 = 16U, /*!< Wdog2 RDC Peripheral. */
|
||||
rdcPdapCcm = 17U, /*!< Ccm RDC Peripheral. */
|
||||
rdcPdapAnatopDig = 18U, /*!< AnatopDig RDC Peripheral. */
|
||||
rdcPdapSnvsHp = 19U, /*!< SnvsHp RDC Peripheral. */
|
||||
rdcPdapEpit1 = 20U, /*!< Epit1 RDC Peripheral. */
|
||||
rdcPdapEpit2 = 21U, /*!< Epit2 RDC Peripheral. */
|
||||
rdcPdapSrc = 22U, /*!< Src RDC Peripheral. */
|
||||
rdcPdapGpc = 23U, /*!< Gpc RDC Peripheral. */
|
||||
rdcPdapIomuxc = 24U, /*!< Iomuxc RDC Peripheral. */
|
||||
rdcPdapIomuxcGpr = 25U, /*!< IomuxcGpr RDC Peripheral. */
|
||||
rdcPdapCanfdCan1 = 26U, /*!< Canfd Can1 RDC Peripheral. */
|
||||
rdcPdapSdma = 27U, /*!< Sdma RDC Peripheral. */
|
||||
rdcPdapCanfdCan2 = 28U, /*!< Canfd Can2 RDC Peripheral. */
|
||||
rdcPdapRdcSema421 = 29U, /*!< Rdc Sema421 RDC Peripheral. */
|
||||
rdcPdapRdcSema422 = 30U, /*!< Rdc Sema422 RDC Peripheral. */
|
||||
rdcPdapRdc = 31U, /*!< Rdc RDC Peripheral. */
|
||||
rdcPdapAipsTz1GlobalEnable1 = 32U, /*!< AipsTz1GlobalEnable1 RDC Peripheral. */
|
||||
rdcPdapAipsTz1GlobalEnable2 = 33U, /*!< AipsTz1GlobalEnable2 RDC Peripheral. */
|
||||
rdcPdapUsb02hPl301 = 34U, /*!< Usb02hPl301 RDC Peripheral. */
|
||||
rdcPdapUsb02hUsb = 35U, /*!< Usb02hUsb RDC Peripheral. */
|
||||
rdcPdapEnet1 = 36U, /*!< Enet1 RDC Peripheral. */
|
||||
rdcPdapMlb2550 = 37U, /*!< Mlb2550 RDC Peripheral. */
|
||||
rdcPdapUsdhc1 = 38U, /*!< Usdhc1 RDC Peripheral. */
|
||||
rdcPdapUsdhc2 = 39U, /*!< Usdhc2 RDC Peripheral. */
|
||||
rdcPdapUsdhc3 = 40U, /*!< Usdhc3 RDC Peripheral. */
|
||||
rdcPdapUsdhc4 = 41U, /*!< Usdhc4 RDC Peripheral. */
|
||||
rdcPdapI2c1 = 42U, /*!< I2c1 RDC Peripheral. */
|
||||
rdcPdapI2c2 = 43U, /*!< I2c2 RDC Peripheral. */
|
||||
rdcPdapI2c3 = 44U, /*!< I2c3 RDC Peripheral. */
|
||||
rdcPdapRomcp = 45U, /*!< Romcp RDC Peripheral. */
|
||||
rdcPdapMmdc = 46U, /*!< Mmdc RDC Peripheral. */
|
||||
rdcPdapEnet2 = 47U, /*!< Enet2 RDC Peripheral. */
|
||||
rdcPdapEim = 48U, /*!< Eim RDC Peripheral. */
|
||||
rdcPdapOcotpCtrlWrapper = 49U, /*!< OcotpCtrlWrapper RDC Peripheral. */
|
||||
rdcPdapCsu = 50U, /*!< Csu RDC Peripheral. */
|
||||
rdcPdapPerfmon1 = 51U, /*!< Perfmon1 RDC Peripheral. */
|
||||
rdcPdapPerfmon2 = 52U, /*!< Perfmon2 RDC Peripheral. */
|
||||
rdcPdapAxiMon = 53U, /*!< AxiMon RDC Peripheral. */
|
||||
rdcPdapTzasc1 = 54U, /*!< Tzasc1 RDC Peripheral. */
|
||||
rdcPdapSai1 = 55U, /*!< Sai1 RDC Peripheral. */
|
||||
rdcPdapAudmux = 56U, /*!< Audmux RDC Peripheral. */
|
||||
rdcPdapSai2 = 57U, /*!< Sai2 RDC Peripheral. */
|
||||
rdcPdapQspi1 = 58U, /*!< Qspi1 RDC Peripheral. */
|
||||
rdcPdapQspi2 = 59U, /*!< Qspi2 RDC Peripheral. */
|
||||
rdcPdapUart2 = 60U, /*!< Uart2 RDC Peripheral. */
|
||||
rdcPdapUart3 = 61U, /*!< Uart3 RDC Peripheral. */
|
||||
rdcPdapUart4 = 62U, /*!< Uart4 RDC Peripheral. */
|
||||
rdcPdapUart5 = 63U, /*!< Uart5 RDC Peripheral. */
|
||||
rdcPdapI2c4 = 64U, /*!< I2c4 RDC Peripheral. */
|
||||
rdcPdapQosc = 65U, /*!< Qosc RDC Peripheral. */
|
||||
rdcPdapCaam = 66U, /*!< Caam RDC Peripheral. */
|
||||
rdcPdapDap = 67U, /*!< Dap RDC Peripheral. */
|
||||
rdcPdapAdc1 = 68U, /*!< Adc1 RDC Peripheral. */
|
||||
rdcPdapAdc2 = 69U, /*!< Adc2 RDC Peripheral. */
|
||||
rdcPdapWdog3 = 70U, /*!< Wdog3 RDC Peripheral. */
|
||||
rdcPdapEcspi5 = 71U, /*!< Ecspi5 RDC Peripheral. */
|
||||
rdcPdapSema4 = 72U, /*!< Sema4 RDC Peripheral. */
|
||||
rdcPdapMuA = 73U, /*!< MuA RDC Peripheral. */
|
||||
rdcPdapCanfdCpu = 74U, /*!< Canfd Cpu RDC Peripheral. */
|
||||
rdcPdapMuB = 75U, /*!< MuB RDC Peripheral. */
|
||||
rdcPdapUart6 = 76U, /*!< Uart6 RDC Peripheral. */
|
||||
rdcPdapPwm5 = 77U, /*!< Pwm5 RDC Peripheral. */
|
||||
rdcPdapPwm6 = 78U, /*!< Pwm6 RDC Peripheral. */
|
||||
rdcPdapPwm7 = 79U, /*!< Pwm7 RDC Peripheral. */
|
||||
rdcPdapPwm8 = 80U, /*!< Pwm8 RDC Peripheral. */
|
||||
rdcPdapAipsTz3GlobalEnable0 = 81U, /*!< AipsTz3GlobalEnable0 RDC Peripheral. */
|
||||
rdcPdapAipsTz3GlobalEnable1 = 82U, /*!< AipsTz3GlobalEnable1 RDC Peripheral. */
|
||||
rdcPdapSpdif = 84U, /*!< Spdif RDC Peripheral. */
|
||||
rdcPdapEcspi1 = 85U, /*!< Ecspi1 RDC Peripheral. */
|
||||
rdcPdapEcspi2 = 86U, /*!< Ecspi2 RDC Peripheral. */
|
||||
rdcPdapEcspi3 = 87U, /*!< Ecspi3 RDC Peripheral. */
|
||||
rdcPdapEcspi4 = 88U, /*!< Ecspi4 RDC Peripheral. */
|
||||
rdcPdapUart1 = 91U, /*!< Uart1 RDC Peripheral. */
|
||||
rdcPdapEsai = 92U, /*!< Esai RDC Peripheral. */
|
||||
rdcPdapSsi1 = 93U, /*!< Ssi1 RDC Peripheral. */
|
||||
rdcPdapSsi2 = 94U, /*!< Ssi2 RDC Peripheral. */
|
||||
rdcPdapSsi3 = 95U, /*!< Ssi3 RDC Peripheral. */
|
||||
rdcPdapAsrc = 96U, /*!< Asrc RDC Peripheral. */
|
||||
rdcPdapSpbaMaMegamix = 98U, /*!< SpbaMaMegamix RDC Peripheral. */
|
||||
rdcPdapGis = 99U, /*!< Gis RDC Peripheral. */
|
||||
rdcPdapDcic1 = 100U, /*!< Dcic1 RDC Peripheral. */
|
||||
rdcPdapDcic2 = 101U, /*!< Dcic2 RDC Peripheral. */
|
||||
rdcPdapCsi1 = 102U, /*!< Csi1 RDC Peripheral. */
|
||||
rdcPdapPxp = 103U, /*!< Pxp RDC Peripheral. */
|
||||
rdcPdapCsi2 = 104U, /*!< Csi2 RDC Peripheral. */
|
||||
rdcPdapLcdif1 = 105U, /*!< Lcdif1 RDC Peripheral. */
|
||||
rdcPdapLcdif2 = 106U, /*!< Lcdif2 RDC Peripheral. */
|
||||
rdcPdapVadc = 107U, /*!< Vadc RDC Peripheral. */
|
||||
rdcPdapVdec = 108U, /*!< Vdec RDC Peripheral. */
|
||||
rdcPdapSpDisplaymix = 109U, /*!< SpDisplaymix RDC Peripheral. */
|
||||
};
|
||||
|
||||
/*! @brief RDC memory region */
|
||||
enum _rdc_mr
|
||||
{
|
||||
rdcMrMmdc = 0U, /*!< alignment 4096 */
|
||||
rdcMrMmdcLast = 7U, /*!< alignment 4096 */
|
||||
rdcMrQspi1 = 8U, /*!< alignment 4096 */
|
||||
rdcMrQspi1Last = 15U, /*!< alignment 4096 */
|
||||
rdcMrQspi2 = 16U, /*!< alignment 4096 */
|
||||
rdcMrQspi2Last = 23U, /*!< alignment 4096 */
|
||||
rdcMrWeim = 24U, /*!< alignment 4096 */
|
||||
rdcMrWeimLast = 31U, /*!< alignment 4096 */
|
||||
rdcMrPcie = 32U, /*!< alignment 4096 */
|
||||
rdcMrPcieLast = 39U, /*!< alignment 4096 */
|
||||
rdcMrOcram = 40U, /*!< alignment 128 */
|
||||
rdcMrOcramLast = 44U, /*!< alignment 128 */
|
||||
rdcMrOcramS = 45U, /*!< alignment 128 */
|
||||
rdcMrOcramSLast = 49U, /*!< alignment 128 */
|
||||
rdcMrOcramL2 = 50U, /*!< alignment 128 */
|
||||
rdcMrOcramL2Last = 54U, /*!< alignment 128 */
|
||||
};
|
||||
|
||||
#endif /* __RDC_DEFS_IMX6SX__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
Loading…
Reference in a new issue