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driver: serial: Add UART support in NPCX series.

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Add UART support for Nuvoton NPCX series. This CL includes:

1. Add UART controller device tree declarations.
2. UART controller driver implementation.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is contained in:
Mulin Chao 2020-07-02 18:15:14 +08:00 committed by Ioannis Glaropoulos
parent 9cb73abbdc
commit 1162747574
10 changed files with 535 additions and 2 deletions
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1
CODEOWNERS
View file

@ -231,6 +231,7 @@
/drivers/serial/uart_xlnx_ps.c @wjliang
/drivers/serial/*xmc4xxx* @parthitce
/drivers/serial/*nuvoton* @ssekar15
/drivers/serial/*npcx* @MulinChao
/drivers/net/ @jukkar @tbursztyka
/drivers/ptp_clock/ @jukkar
/drivers/pwm/*rv32m1* @henrikbrixandersen

1
drivers/serial/CMakeLists.txt
View file

@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_LITEUART uart_liteuart.c)
zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c)
zephyr_library_sources_ifdef(CONFIG_UART_XLNX_PS uart_xlnx_ps.c)
zephyr_library_sources_ifdef(CONFIG_UART_XMC4XXX uart_xmc4xxx.c)
zephyr_library_sources_ifdef(CONFIG_UART_NPCX uart_npcx.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)

2
drivers/serial/Kconfig
View file

@ -128,4 +128,6 @@ source "drivers/serial/Kconfig.xmc4xxx"
source "drivers/serial/Kconfig.lpc11u6x"
source "drivers/serial/Kconfig.npcx"
endif # SERIAL

14
drivers/serial/Kconfig.npcx Normal file
View file

@ -0,0 +1,14 @@
# NPCX UART driver configuration options
# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config UART_NPCX
bool "Nuvoton NPCX embedd controller (EC) serial driver"
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
depends on SOC_FAMILY_NPCX
help
This option enables the UART driver for NPCX family of
processors.
Say y if you wish to use serial port on NPCX MCU.

392
drivers/serial/uart_npcx.c Normal file
View file

@ -0,0 +1,392 @@
/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_uart
#include <assert.h>
#include <drivers/uart.h>
#include <drivers/clock_control.h>
#include <kernel.h>
#include <soc.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(uart_npcx, LOG_LEVEL_ERR);
/* Driver config */
struct uart_npcx_config {
struct uart_device_config uconf;
/* clock configuration */
struct npcx_clk_cfg clk_cfg;
/* pinmux configuration */
const uint8_t alts_size;
const struct npcx_alt *alts_list;
};
/* Driver data */
struct uart_npcx_data {
/* Baud rate */
uint32_t baud_rate;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t user_cb;
void *user_data;
#endif
};
/* Driver convenience defines */
#define DRV_CONFIG(dev) \
((const struct uart_npcx_config *)(dev)->config)
#define DRV_DATA(dev) \
((struct uart_npcx_data *)(dev)->data)
#define HAL_INSTANCE(dev) \
(struct uart_reg_t *)(DRV_CONFIG(dev)->uconf.base)
/* UART local functions */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int uart_npcx_tx_fifo_ready(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* True if the Tx FIFO is not completely full */
return !(GET_FIELD(inst->UFTSTS, NPCX_UFTSTS_TEMPTY_LVL) == 0);
}
static int uart_npcx_rx_fifo_available(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* True if at least one byte is in the Rx FIFO */
return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);
}
static void uart_npcx_dis_all_tx_interrupts(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Disable all Tx interrupts */
inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
BIT(NPCX_UFTCTL_TEMPTY_EN) |
BIT(NPCX_UFTCTL_NXMIPEN));
}
static void uart_npcx_clear_rx_fifo(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
uint8_t scratch;
/* Read all dummy bytes out from Rx FIFO */
while (uart_npcx_rx_fifo_available(dev))
scratch = inst->URBUF;
}
#endif
/* UART api functions */
static int uart_npcx_poll_in(struct device *dev, unsigned char *c)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Rx single byte buffer is not full */
if (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_RBF))
return -1;
*c = inst->URBUF;
return 0;
}
static void uart_npcx_poll_out(struct device *dev, unsigned char c)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Wait while Tx single byte buffer is ready to send */
while (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_TBE))
continue;
inst->UTBUF = c;
}
static int uart_npcx_err_check(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
uint32_t err = 0U;
uint8_t stat = inst->USTAT;
if (IS_BIT_SET(stat, NPCX_USTAT_DOE))
err |= UART_ERROR_OVERRUN;
if (IS_BIT_SET(stat, NPCX_USTAT_PE))
err |= UART_ERROR_PARITY;
if (IS_BIT_SET(stat, NPCX_USTAT_FE))
err |= UART_ERROR_FRAMING;
return err;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int uart_npcx_fifo_fill(struct device *dev, const uint8_t *tx_data,
int size)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
uint8_t tx_bytes = 0U;
/* If Tx FIFO is still ready to send */
while ((size - tx_bytes > 0) && uart_npcx_tx_fifo_ready(dev)) {
/* Put a character into Tx FIFO */
inst->UTBUF = tx_data[tx_bytes++];
}
return tx_bytes;
}
static int uart_npcx_fifo_read(struct device *dev, uint8_t *rx_data,
const int size)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
unsigned int rx_bytes = 0U;
/* If least one byte is in the Rx FIFO */
while ((size - rx_bytes > 0) && uart_npcx_rx_fifo_available(dev)) {
/* Receive one byte from Rx FIFO */
rx_data[rx_bytes++] = inst->URBUF;
}
return rx_bytes;
}
static void uart_npcx_irq_tx_enable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UFTCTL |= BIT(NPCX_UFTCTL_TEMPTY_EN);
}
static void uart_npcx_irq_tx_disable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_EN));
}
static int uart_npcx_irq_tx_ready(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Tx interrupt is enable and its FIFO is ready to send (not full) */
return (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_TEMPTY_EN) &&
uart_npcx_tx_fifo_ready(dev));
}
static int uart_npcx_irq_tx_complete(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Tx FIFO is empty or last byte is sending */
return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);
}
static void uart_npcx_irq_rx_enable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UFRCTL |= BIT(NPCX_UFRCTL_RNEMPTY_EN);
}
static void uart_npcx_irq_rx_disable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UFRCTL &= ~(BIT(NPCX_UFRCTL_RNEMPTY_EN));
}
static int uart_npcx_irq_rx_ready(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
/* Rx interrupt is enable and at least one byte is in its FIFO */
return (IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN) &&
uart_npcx_rx_fifo_available(dev));
}
static void uart_npcx_irq_err_enable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UICTRL |= BIT(NPCX_UICTRL_EEI);
}
static void uart_npcx_irq_err_disable(struct device *dev)
{
struct uart_reg_t *inst = HAL_INSTANCE(dev);
inst->UICTRL &= ~(BIT(NPCX_UICTRL_EEI));
}
static int uart_npcx_irq_is_pending(struct device *dev)
{
return (uart_npcx_irq_tx_ready(dev)
|| uart_npcx_irq_rx_ready(dev));
}
static int uart_npcx_irq_update(struct device *dev)
{
ARG_UNUSED(dev);
return 1;
}
static void uart_npcx_irq_callback_set(struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct uart_npcx_data *data = DRV_DATA(dev);
data->user_cb = cb;
data->user_data = cb_data;
}
static void uart_npcx_isr(void *arg)
{
struct device *dev = arg;
struct uart_npcx_data *data = DRV_DATA(dev);
if (data->user_cb) {
data->user_cb(dev, data->user_data);
}
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
/* UART driver registration */
static const struct uart_driver_api uart_npcx_driver_api = {
.poll_in = uart_npcx_poll_in,
.poll_out = uart_npcx_poll_out,
.err_check = uart_npcx_err_check,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_npcx_fifo_fill,
.fifo_read = uart_npcx_fifo_read,
.irq_tx_enable = uart_npcx_irq_tx_enable,
.irq_tx_disable = uart_npcx_irq_tx_disable,
.irq_tx_ready = uart_npcx_irq_tx_ready,
.irq_tx_complete = uart_npcx_irq_tx_complete,
.irq_rx_enable = uart_npcx_irq_rx_enable,
.irq_rx_disable = uart_npcx_irq_rx_disable,
.irq_rx_ready = uart_npcx_irq_rx_ready,
.irq_err_enable = uart_npcx_irq_err_enable,
.irq_err_disable = uart_npcx_irq_err_disable,
.irq_is_pending = uart_npcx_irq_is_pending,
.irq_update = uart_npcx_irq_update,
.irq_callback_set = uart_npcx_irq_callback_set,
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
static int uart_npcx_init(struct device *dev)
{
const struct uart_npcx_config *config = DRV_CONFIG(dev);
const struct uart_npcx_data *data = DRV_DATA(dev);
struct uart_reg_t *inst = HAL_INSTANCE(dev);
struct device *clk_dev = device_get_binding(NPCX_CLOCK_CONTROL_NAME);
uint32_t uart_rate;
/* Turn on device clock first */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg) != 0) {
return -EIO;
}
/*
* If apb2's clock is not 15MHz, we need to find the other optimized
* values of UPSR and UBAUD for baud rate 115200.
*/
if (clock_control_get_rate(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg, &uart_rate) < 0) {
LOG_ERR("UART clock rate get error.");
}
__ASSERT(uart_rate == 15000000, "Unsupported apb2 clock for UART!");
/* Fix baud rate to 115200 */
if (data->baud_rate == 115200) {
inst->UPSR = 0x38;
inst->UBAUD = 0x01;
} else
return -EINVAL;
/*
* 8-N-1, FIFO enabled. Must be done after setting
* the divisor for the new divisor to take effect.
*/
inst->UFRS = 0x00;
/* Initialize UART FIFO if mode is interrupt driven */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
/* Enable the UART FIFO mode */
inst->UMDSL |= BIT(NPCX_UMDSL_FIFO_MD);
/* Disable all UART tx FIFO interrupts */
uart_npcx_dis_all_tx_interrupts(dev);
/* Clear UART rx FIFO */
uart_npcx_clear_rx_fifo(dev);
/* Configure UART interrupts */
config->uconf.irq_config_func(dev);
#endif
/* Configure pin-mux for uart device */
soc_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
return 0;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
#define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst) \
static void uart_npcx_irq_config_##inst(struct device *dev)
#define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst) \
.irq_config_func = uart_npcx_irq_config_##inst,
#define NPCX_UART_IRQ_CONFIG_FUNC(inst) \
static void uart_npcx_irq_config_##inst(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
uart_npcx_isr, \
DEVICE_GET(uart_npcx_##inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
}
#else
#define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst)
#define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst)
#define NPCX_UART_IRQ_CONFIG_FUNC(inst)
#endif
#define NPCX_UART_INIT(inst) \
NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst); \
\
static const struct npcx_alt uart_alts##inst[] = \
DT_NPCX_ALT_ITEMS_LIST(inst); \
\
static const struct uart_npcx_config uart_npcx_cfg_##inst = { \
.uconf = { \
.base = (uint8_t *)DT_INST_REG_ADDR(inst), \
NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst) \
}, \
.clk_cfg = DT_NPCX_CLK_CFG_ITEM(inst), \
.alts_size = ARRAY_SIZE(uart_alts##inst), \
.alts_list = uart_alts##inst, \
}; \
\
static struct uart_npcx_data uart_npcx_data_##inst = { \
.baud_rate = DT_INST_PROP(inst, current_speed) \
}; \
\
DEVICE_AND_API_INIT(uart_npcx_##inst, DT_INST_LABEL(inst), \
&uart_npcx_init, \
&uart_npcx_data_##inst, &uart_npcx_cfg_##inst, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&uart_npcx_driver_api); \
\
NPCX_UART_IRQ_CONFIG_FUNC(inst)
DT_INST_FOREACH_STATUS_OKAY(NPCX_UART_INIT)

20
dts/arm/nuvoton/npcx7m6fb.dtsi
View file

@ -60,6 +60,26 @@
#lvol-cells = <2>;
label = "SCFG";
};
uart1: serial@400c4000 {
compatible = "nuvoton,npcx-uart";
reg = <0x400C4000 0x2000>;
interrupts = <33 0>;
clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
pinctrl = <&alta_uart1_sl1>; /* PIN10.11 */
status = "disabled";
label = "UART_1";
};
uart2: serial@400c6000 {
compatible = "nuvoton,npcx-uart";
reg = <0x400C6000 0x2000>;
interrupts = <32 0>;
clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>;
pinctrl = <&alta_uart2_sl>; /* PIN75.86 */
status = "disabled";
label = "UART_2";
};
};
};

18
dts/bindings/serial/nuvoton,npcx-uart.yaml Normal file
View file

@ -0,0 +1,18 @@
# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
description: Nuvoton, NPCX-UART node
compatible: "nuvoton,npcx-uart"
include: uart-controller.yaml
properties:
reg:
required: true
clocks:
required: true
pinctrl:
type: phandles
required: true
description: configurations of pinmux controllers

78
soc/arm/nuvoton_npcx/common/reg/reg_def.h
View file

@ -182,6 +182,80 @@ struct scfg_reg_t {
#define NPCX_DEVPU0_I2C3_0_PUE 6
#define NPCX_DEVPU1_F_SPI_PUD_EN 7
/*
* Universal Asynchronous Receiver-Transmitter (UART) device registers
*/
struct uart_reg_t {
/* 0x000: Transmit Data Buffer */
volatile uint8_t UTBUF;
volatile uint8_t reserved1;
/* 0x002: Receive Data Buffer */
volatile uint8_t URBUF;
volatile uint8_t reserved2;
/* 0x004: Interrupt Control */
volatile uint8_t UICTRL;
volatile uint8_t reserved3;
/* 0x006: Status */
volatile uint8_t USTAT;
volatile uint8_t reserved4;
/* 0x008: Frame Select */
volatile uint8_t UFRS;
volatile uint8_t reserved5;
/* 0x00A: Mode Select */
volatile uint8_t UMDSL;
volatile uint8_t reserved6;
/* 0x00C: Baud Rate Divisor */
volatile uint8_t UBAUD;
volatile uint8_t reserved7;
/* 0x00E: Baud Rate Prescaler */
volatile uint8_t UPSR;
volatile uint8_t reserved8[17];
/* 0x020: FIFO Mode Transmit Status */
volatile uint8_t UFTSTS;
volatile uint8_t reserved9;
/* 0x022: FIFO Mode Receive Status */
volatile uint8_t UFRSTS;
volatile uint8_t reserved10;
/* 0x024: FIFO Mode Transmit Control */
volatile uint8_t UFTCTL;
volatile uint8_t reserved11;
/* 0x026: FIFO Mode Receive Control */
volatile uint8_t UFRCTL;
};
/* UART register fields */
#define NPCX_UICTRL_TBE 0
#define NPCX_UICTRL_RBF 1
#define NPCX_UICTRL_ETI 5
#define NPCX_UICTRL_ERI 6
#define NPCX_UICTRL_EEI 7
#define NPCX_USTAT_PE 0
#define NPCX_USTAT_FE 1
#define NPCX_USTAT_DOE 2
#define NPCX_USTAT_ERR 3
#define NPCX_USTAT_BKD 4
#define NPCX_USTAT_RB9 5
#define NPCX_USTAT_XMIP 6
#define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
#define NPCX_UFRS_STP 2
#define NPCX_UFRS_XB9 3
#define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
#define NPCX_UFRS_PEN 6
#define NPCX_UMDSL_FIFO_MD 0
#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
#define NPCX_UFTSTS_TEMPTY_LVL_STS 5
#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
#define NPCX_UFTSTS_NXMIP 7
#define NPCX_UFRSTS_RFULL_LVL_STS 5
#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
#define NPCX_UFRSTS_ERR 7
#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
#define NPCX_UFTCTL_TEMPTY_LVL_EN 5
#define NPCX_UFTCTL_TEMPTY_EN 6
#define NPCX_UFTCTL_NXMIPEN 7
#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
#define NPCX_UFRCTL_RFULL_LVL_EN 5
#define NPCX_UFRCTL_RNEMPTY_EN 6
#define NPCX_UFRCTL_ERR_EN 7
#endif /* _NUVOTON_NPCX_REG_DEF_H */

6
soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series
View file

@ -23,6 +23,12 @@ config PINMUX_NPCX
help
Enable support for NPCX pinmux controller driver.
config UART_NPCX
default y
depends on SERIAL
help
Enable support for NPCX UART driver.
source "soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7*"
endif # SOC_SERIES_NPCX7

5
soc/arm/nuvoton_npcx/npcx7/soc.c
View file

@ -37,3 +37,8 @@ NPCX_REG_OFFSET_CHECK(scfg_reg_t, DEV_CTL4, 0x006);
NPCX_REG_OFFSET_CHECK(scfg_reg_t, DEVALT0, 0x010);
NPCX_REG_OFFSET_CHECK(scfg_reg_t, LV_GPIO_CTL0, 0x02A);
/* UART register structure check */
NPCX_REG_SIZE_CHECK(uart_reg_t, 0x027);
NPCX_REG_OFFSET_CHECK(uart_reg_t, UPSR, 0x00E);
NPCX_REG_OFFSET_CHECK(uart_reg_t, UFTSTS, 0x020);
NPCX_REG_OFFSET_CHECK(uart_reg_t, UFRCTL, 0x026);