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dts: arm: st: add reset properties to sdmmc nodes

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This allows the sdmmc driver to reset the peripheral during initialisation.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This commit is contained in:
Armin Brauns 2023-01-13 16:44:59 +01:00 committed by Carles Cufí
parent 592adeeac4
commit 149ab4f956
9 changed files with 13 additions and 1 deletions
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1
dts/arm/st/f4/stm32f4.dtsi
View file

@ -530,6 +530,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
resets = <&rctl STM32_RESET(APB2, 11U)>;
interrupts = <49 0>;
status = "disabled";
};

1
dts/arm/st/f7/stm32f7.dtsi
View file

@ -726,6 +726,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
resets = <&rctl STM32_RESET(APB2, 11U)>;
interrupts = <49 0>;
status = "disabled";
};

1
dts/arm/st/f7/stm32f723.dtsi
View file

@ -42,6 +42,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <103 0>;
status = "disabled";
};

1
dts/arm/st/f7/stm32f767.dtsi
View file

@ -83,6 +83,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <103 0>;
status = "disabled";
};

2
dts/arm/st/h7/stm32h7.dtsi
View file

@ -817,6 +817,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x52007000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>;
resets = <&rctl STM32_RESET(AHB3, 16U)>;
interrupts = <49 0>;
status = "disabled";
};
@ -825,6 +826,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x48022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
resets = <&rctl STM32_RESET(AHB2, 8U)>;
interrupts = <124 0>;
status = "disabled";
};

1
dts/arm/st/l4/stm32l471.dtsi
View file

@ -238,6 +238,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x40012800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
resets = <&rctl STM32_RESET(APB2, 10U)>;
interrupts = <49 0>;
status = "disabled";
};

1
dts/arm/st/l4/stm32l4r5.dtsi
View file

@ -316,6 +316,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x50062400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>;
resets = <&rctl STM32_RESET(AHB2, 22U)>;
interrupts = <49 0>;
status = "disabled";
};

1
dts/arm/st/l5/stm32l5.dtsi
View file

@ -361,6 +361,7 @@
compatible = "st,stm32-sdmmc";
reg = <0x420c8000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00400000>;
resets = <&rctl STM32_RESET(AHB2, 22U)>;
interrupts = <78 0>;
status = "disabled";
};

5
dts/bindings/mmc/st,stm32-sdmmc.yaml
View file

@ -2,7 +2,7 @@ description: stm32 sdmmc disk access
compatible: "st,stm32-sdmmc"
include: [mmc.yaml, pinctrl-device.yaml]
include: [mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
properties:
clocks:
@ -11,6 +11,9 @@ properties:
reg:
required: true
resets:
required: true
pinctrl-0:
required: true