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spi: intel: Fixing how speed is set

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This was failing, the documentationg provides numbers only telling at
one places these are hexadecimal values. So switching to hexadecimal.
Then DDS rate retrieving macro was bogus, so fixing it.
And adding debug output about the DDS rate and the clock ratio.

Change-Id: I9cc414796fbd7f7123f1f406c6bce7ffacf641e8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2015-10-09 17:14:58 +03:00 committed by Anas Nashif
parent 93f38d26c2
commit 15058e21ef
3 changed files with 37 additions and 33 deletions
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4
drivers/spi/intel_spi.c
View file

@ -256,6 +256,10 @@ static int spi_intel_configure(struct device *dev, struct spi_config *config)
write_sscr0(spi->sscr0, info->regs);
write_sscr1(spi->sscr1, info->regs);
DBG("spi_intel_configure: DDS_RATE: 0x%x SCR: %d\n",
INTEL_SPI_DSS_RATE(config->max_sys_freq),
INTEL_SPI_SSCR0_SCR(config->max_sys_freq));
/* Word size and clock rate */
spi->sscr0 = INTEL_SPI_SSCR0_DSS(SPI_WORD_SIZE_GET(flags)) |
INTEL_SPI_SSCR0_SCR(config->max_sys_freq);

2
drivers/spi/intel_spi_priv.h
View file

@ -88,6 +88,6 @@
/* DSS_RATE settings */
#define INTEL_SPI_DSS_RATE(__msf) \
((__msf && (INTEL_SPI_DDS_RATE_MASK)) >> 8)
((__msf & (INTEL_SPI_DDS_RATE_MASK)) >> 8)
#endif /* __INTEL_SPI_PRIV_H__ */

64
include/drivers/spi/intel_spi.h
View file

@ -77,38 +77,38 @@ struct spi_intel_data {
};
/* SPI Maximum supported system frequencies */
#define SPI_MAX_CLK_FREQ_25MHZ ((800000 << 8))
#define SPI_MAX_CLK_FREQ_20MHz ((666666 << 8) | 1)
#define SPI_MAX_CLK_FREQ_166667KHZ ((800000 << 8) | 2)
#define SPI_MAX_CLK_FREQ_13333KHZ ((666666 << 8) | 2)
#define SPI_MAX_CLK_FREQ_12500KHZ ((200000 << 8))
#define SPI_MAX_CLK_FREQ_10MHZ ((800000 << 8) | 4)
#define SPI_MAX_CLK_FREQ_8MHZ ((666666 << 8) | 4)
#define SPI_MAX_CLK_FREQ_6250HZ ((400000 << 8) | 3)
#define SPI_MAX_CLK_FREQ_5MHZ ((400000 << 8) | 4)
#define SPI_MAX_CLK_FREQ_4MHZ ((666666 << 8) | 9)
#define SPI_MAX_CLK_FREQ_3125KHZ ((80000 << 8))
#define SPI_MAX_CLK_FREQ_2500KHZ ((400000 << 8) | 9)
#define SPI_MAX_CLK_FREQ_2MHZ ((666666 << 8) | 19)
#define SPI_MAX_CLK_FREQ_1563KHZ ((40000 << 8))
#define SPI_MAX_CLK_FREQ_1250KHZ ((200000 << 8) | 9)
#define SPI_MAX_CLK_FREQ_1MHZ ((400000 << 8) | 24)
#define SPI_MAX_CLK_FREQ_800KHZ ((666666 << 8) | 49)
#define SPI_MAX_CLK_FREQ_781KHZ ((20000 << 8))
#define SPI_MAX_CLK_FREQ_625KHZ ((200000 << 8) | 19)
#define SPI_MAX_CLK_FREQ_500KHZ ((400000 << 8) | 49)
#define SPI_MAX_CLK_FREQ_400KHZ ((666666 << 8) | 99)
#define SPI_MAX_CLK_FREQ_390KHZ ((10000 << 8))
#define SPI_MAX_CLK_FREQ_250KHZ ((400000 << 8) | 99)
#define SPI_MAX_CLK_FREQ_200KHZ ((666666 << 8) | 199)
#define SPI_MAX_CLK_FREQ_195KHZ ((8000 << 8))
#define SPI_MAX_CLK_FREQ_125KHZ ((100000 << 8) | 49)
#define SPI_MAX_CLK_FREQ_100KHZ ((200000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_50KHZ ((100000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_20KHZ ((80000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_10KHZ ((20000 << 8) | 77)
#define SPI_MAX_CLK_FREQ_5KHZ ((20000 << 8) | 154)
#define SPI_MAX_CLK_FREQ_1KHZ ((8000 << 8) | 194)
#define SPI_MAX_CLK_FREQ_25MHZ ((0x800000 << 8))
#define SPI_MAX_CLK_FREQ_20MHz ((0x666666 << 8) | 1)
#define SPI_MAX_CLK_FREQ_166667KHZ ((0x800000 << 8) | 2)
#define SPI_MAX_CLK_FREQ_13333KHZ ((0x666666 << 8) | 2)
#define SPI_MAX_CLK_FREQ_12500KHZ ((0x200000 << 8))
#define SPI_MAX_CLK_FREQ_10MHZ ((0x800000 << 8) | 4)
#define SPI_MAX_CLK_FREQ_8MHZ ((0x666666 << 8) | 4)
#define SPI_MAX_CLK_FREQ_6250HZ ((0x400000 << 8) | 3)
#define SPI_MAX_CLK_FREQ_5MHZ ((0x400000 << 8) | 4)
#define SPI_MAX_CLK_FREQ_4MHZ ((0x666666 << 8) | 9)
#define SPI_MAX_CLK_FREQ_3125KHZ ((0x80000 << 8))
#define SPI_MAX_CLK_FREQ_2500KHZ ((0x400000 << 8) | 9)
#define SPI_MAX_CLK_FREQ_2MHZ ((0x666666 << 8) | 19)
#define SPI_MAX_CLK_FREQ_1563KHZ ((0x40000 << 8))
#define SPI_MAX_CLK_FREQ_1250KHZ ((0x200000 << 8) | 9)
#define SPI_MAX_CLK_FREQ_1MHZ ((0x400000 << 8) | 24)
#define SPI_MAX_CLK_FREQ_800KHZ ((0x666666 << 8) | 49)
#define SPI_MAX_CLK_FREQ_781KHZ ((0x20000 << 8))
#define SPI_MAX_CLK_FREQ_625KHZ ((0x200000 << 8) | 19)
#define SPI_MAX_CLK_FREQ_500KHZ ((0x400000 << 8) | 49)
#define SPI_MAX_CLK_FREQ_400KHZ ((0x666666 << 8) | 99)
#define SPI_MAX_CLK_FREQ_390KHZ ((0x10000 << 8))
#define SPI_MAX_CLK_FREQ_250KHZ ((0x400000 << 8) | 99)
#define SPI_MAX_CLK_FREQ_200KHZ ((0x666666 << 8) | 199)
#define SPI_MAX_CLK_FREQ_195KHZ ((0x8000 << 8))
#define SPI_MAX_CLK_FREQ_125KHZ ((0x100000 << 8) | 49)
#define SPI_MAX_CLK_FREQ_100KHZ ((0x200000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_50KHZ ((0x100000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_20KHZ ((0x80000 << 8) | 124)
#define SPI_MAX_CLK_FREQ_10KHZ ((0x20000 << 8) | 77)
#define SPI_MAX_CLK_FREQ_5KHZ ((0x20000 << 8) | 154)
#define SPI_MAX_CLK_FREQ_1KHZ ((0x8000 << 8) | 194)
#ifdef __cplusplus
}