drivers: can: nxp_s32_canxl: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of devicetree instance-based macros because the NXP S32 HAL relies on an index-based approach, requiring knowledge of the peripheral instance index during both compilation and runtime, and this index might not align with the devicetree instance index. The proposed solution in this patch eliminates this limitation by determining the peripheral instance index during compilation through macrobatics and defining the driver's ISR within the shim driver itself. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles
Carles Cufí
parent
3508cd609c
commit
1572ea16fc
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@ -933,6 +933,20 @@ static int can_nxp_s32_init(const struct device *dev)
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return 0;
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}
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static void can_nxp_s32_isr_rx_tx(const struct device *dev)
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{
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const struct can_nxp_s32_config *config = dev->config;
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Canexcel_Ip_RxTxIRQHandler(config->instance);
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}
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static void can_nxp_s32_isr_error(const struct device *dev)
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{
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const struct can_nxp_s32_config *config = dev->config;
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Canexcel_Ip_ErrIRQHandler(config->instance);
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}
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static const struct can_driver_api can_nxp_s32_driver_api = {
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.get_capabilities = can_nxp_s32_get_capabilities,
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.start = can_nxp_s32_start,
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@ -983,19 +997,13 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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#endif
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};
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#define CAN_NXP_S32_NODE(n) DT_NODELABEL(can##n)
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#define CAN_NXP_S32_IRQ_HANDLER(n, irq_name) DT_CAT5(CANXL, n, _, irq_name, Handler)
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#define _CAN_NXP_S32_IRQ_CONFIG(node_id, prop, idx, n) \
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#define _CAN_NXP_S32_IRQ_CONFIG(node_id, prop, idx) \
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do { \
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extern void (CAN_NXP_S32_IRQ_HANDLER(n, \
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DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)))(void); \
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IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
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DT_IRQ_BY_IDX(node_id, idx, priority), \
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CAN_NXP_S32_IRQ_HANDLER(n, \
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UTIL_CAT(can_nxp_s32_isr_, \
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DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)), \
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NULL, \
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DEVICE_DT_GET(node_id), \
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DT_IRQ_BY_IDX(node_id, idx, flags)); \
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irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq)); \
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} while (false);
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@ -1003,15 +1011,14 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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#define CAN_NXP_S32_IRQ_CONFIG(n) \
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static void can_irq_config_##n(void) \
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{ \
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DT_FOREACH_PROP_ELEM_VARGS(CAN_NXP_S32_NODE(n), interrupt_names, \
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_CAN_NXP_S32_IRQ_CONFIG, n); \
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DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, _CAN_NXP_S32_IRQ_CONFIG); \
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}
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#define CAN_NXP_S32_ERR_CALLBACK(n) \
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void nxp_s32_can_##n##_err_callback(uint8 instance, Canexcel_Ip_EventType eventType,\
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uint32 u32SysStatus, const Canexcel_Ip_StateType *canexcelState) \
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{ \
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const struct device *dev = DEVICE_DT_GET(CAN_NXP_S32_NODE(n)); \
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const struct device *dev = DEVICE_DT_INST_GET(n); \
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can_nxp_s32_err_callback(dev, eventType, u32SysStatus, canexcelState); \
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}
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@ -1019,18 +1026,18 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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void nxp_s32_can_##n##_ctrl_callback(uint8 instance, Canexcel_Ip_EventType eventType,\
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uint32 buffIdx, const Canexcel_Ip_StateType *canexcelState) \
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{ \
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const struct device *dev = DEVICE_DT_GET(CAN_NXP_S32_NODE(n)); \
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const struct device *dev = DEVICE_DT_INST_GET(n); \
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can_nxp_s32_ctrl_callback(dev, eventType, buffIdx, canexcelState); \
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}
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#if defined(CONFIG_CAN_FD_MODE)
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#define CAN_NXP_S32_TIMING_DATA_CONFIG(n) \
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.bitrate_data = DT_PROP(CAN_NXP_S32_NODE(n), bus_speed_data), \
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.sjw_data = DT_PROP(CAN_NXP_S32_NODE(n), sjw_data), \
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.prop_seg_data = DT_PROP_OR(CAN_NXP_S32_NODE(n), prop_seg_data, 0), \
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.phase_seg1_data = DT_PROP_OR(CAN_NXP_S32_NODE(n), phase_seg1_data, 0), \
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.phase_seg2_data = DT_PROP_OR(CAN_NXP_S32_NODE(n), phase_seg2_data, 0), \
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.sample_point_data = DT_PROP_OR(CAN_NXP_S32_NODE(n), sample_point_data, 0),
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.bitrate_data = DT_INST_PROP(n, bus_speed_data), \
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.sjw_data = DT_INST_PROP(n, sjw_data), \
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.prop_seg_data = DT_INST_PROP_OR(n, prop_seg_data, 0), \
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.phase_seg1_data = DT_INST_PROP_OR(n, phase_seg1_data, 0), \
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.phase_seg2_data = DT_INST_PROP_OR(n, phase_seg2_data, 0), \
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.sample_point_data = DT_INST_PROP_OR(n, sample_point_data, 0),
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#define CAN_NXP_S32_FD_MODE 1
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#define CAN_NXP_S32_BRS 1
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#else
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@ -1045,11 +1052,17 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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#define CAN_NXP_S32_CTRL_OPTIONS 0
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#endif
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#define CAN_NXP_S32_HW_INSTANCE_CHECK(i, n) \
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((DT_INST_REG_ADDR(n) == IP_CANXL_##i##__SIC_BASE) ? i : 0)
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#define CAN_NXP_S32_HW_INSTANCE(n) \
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LISTIFY(__DEBRACKET CANXL_SIC_INSTANCE_COUNT, CAN_NXP_S32_HW_INSTANCE_CHECK, (|), n)
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#define CAN_NXP_S32_INIT_DEVICE(n) \
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CAN_NXP_S32_CTRL_CALLBACK(n) \
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CAN_NXP_S32_ERR_CALLBACK(n) \
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CAN_NXP_S32_IRQ_CONFIG(n) \
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PINCTRL_DT_DEFINE(CAN_NXP_S32_NODE(n)); \
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PINCTRL_DT_INST_DEFINE(n); \
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Canexcel_Ip_ConfigType can_nxp_s32_default_config##n = { \
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.rx_mbdesc = (uint8)CONFIG_CAN_NXP_S32_MAX_RX, \
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.tx_mbdesc = (uint8)CONFIG_CAN_NXP_S32_MAX_TX, \
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@ -1069,27 +1082,26 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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.rx_msg = rx_msg_##n, \
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}; \
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static struct can_nxp_s32_config can_nxp_s32_config_##n = { \
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.base_sic = (CANXL_SIC_Type *) \
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DT_REG_ADDR_BY_NAME(CAN_NXP_S32_NODE(n), sic), \
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.base_sic = (CANXL_SIC_Type *)DT_INST_REG_ADDR_BY_NAME(n, sic), \
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.base_grp_ctrl = (CANXL_GRP_CONTROL_Type *) \
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DT_REG_ADDR_BY_NAME(CAN_NXP_S32_NODE(n), grp_ctrl), \
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DT_INST_REG_ADDR_BY_NAME(n, grp_ctrl), \
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.base_dsc_ctrl = (CANXL_DSC_CONTROL_Type *) \
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DT_REG_ADDR_BY_NAME(CAN_NXP_S32_NODE(n), dsc_ctrl), \
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.instance = n, \
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(CAN_NXP_S32_NODE(n))), \
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DT_INST_REG_ADDR_BY_NAME(n, dsc_ctrl), \
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.instance = CAN_NXP_S32_HW_INSTANCE(n), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_CLOCKS_CELL(CAN_NXP_S32_NODE(n), name), \
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.bitrate = DT_PROP(CAN_NXP_S32_NODE(n), bus_speed), \
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.sjw = DT_PROP(CAN_NXP_S32_NODE(n), sjw), \
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.prop_seg = DT_PROP_OR(CAN_NXP_S32_NODE(n), prop_seg, 0), \
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.phase_seg1 = DT_PROP_OR(CAN_NXP_S32_NODE(n), phase_seg1, 0), \
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.phase_seg2 = DT_PROP_OR(CAN_NXP_S32_NODE(n), phase_seg2, 0), \
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.sample_point = DT_PROP_OR(CAN_NXP_S32_NODE(n), sample_point, 0), \
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DT_INST_CLOCKS_CELL(n, name), \
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.bitrate = DT_INST_PROP(n, bus_speed), \
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.sjw = DT_INST_PROP(n, sjw), \
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.prop_seg = DT_INST_PROP_OR(n, prop_seg, 0), \
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.phase_seg1 = DT_INST_PROP_OR(n, phase_seg1, 0), \
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.phase_seg2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
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.sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
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CAN_NXP_S32_TIMING_DATA_CONFIG(n) \
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.max_bitrate = DT_CAN_TRANSCEIVER_MAX_BITRATE(CAN_NXP_S32_NODE(n), \
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.max_bitrate = DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(n, \
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CAN_NXP_S32_MAX_BITRATE), \
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.phy = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(CAN_NXP_S32_NODE(n), phys)), \
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.pin_cfg = PINCTRL_DT_DEV_CONFIG_GET(CAN_NXP_S32_NODE(n)), \
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.phy = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(n, phys)), \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.can_cfg = (Canexcel_Ip_ConfigType *)&can_nxp_s32_default_config##n, \
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.irq_config_func = can_irq_config_##n \
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}; \
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@ -1097,19 +1109,13 @@ static const struct can_driver_api can_nxp_s32_driver_api = {
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{ \
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return can_nxp_s32_init(dev); \
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} \
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CAN_DEVICE_DT_DEFINE(CAN_NXP_S32_NODE(n), \
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can_nxp_s32_##n##_init, \
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NULL, \
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&can_nxp_s32_data_##n, \
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&can_nxp_s32_config_##n, \
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POST_KERNEL, \
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CONFIG_CAN_INIT_PRIORITY, \
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&can_nxp_s32_driver_api);
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CAN_DEVICE_DT_INST_DEFINE(n, \
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can_nxp_s32_##n##_init, \
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NULL, \
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&can_nxp_s32_data_##n, \
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&can_nxp_s32_config_##n, \
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POST_KERNEL, \
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CONFIG_CAN_INIT_PRIORITY, \
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&can_nxp_s32_driver_api);
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#if DT_NODE_HAS_STATUS(CAN_NXP_S32_NODE(0), okay)
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CAN_NXP_S32_INIT_DEVICE(0)
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#endif
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#if DT_NODE_HAS_STATUS(CAN_NXP_S32_NODE(1), okay)
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CAN_NXP_S32_INIT_DEVICE(1)
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#endif
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DT_INST_FOREACH_STATUS_OKAY(CAN_NXP_S32_INIT_DEVICE)
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@ -700,7 +700,7 @@
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status = "disabled";
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
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interrupt-names = "rx_tx", "error";
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clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
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};
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@ -713,7 +713,7 @@
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status = "disabled";
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
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interrupt-names = "rx_tx", "error";
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clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
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};
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};
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