nrf52_bsim: docs: Minor update

The EGU has been modelled now. Add it to the list of
supported peripherals.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>

boards/posix/nrf52_bsim/doc/index.rst

@@ -25,6 +25,7 @@ This board models some of the NRF52 SOC peripherals:
 * Accelerated address resolver
 * Clock control
 * PPI (Programmable Peripheral Interconnect)
+* EGU (Event Generator Unit)
 
 The nrf52_bsim board definition uses the POSIX architecture to
 run applications natively on the development system, this has the benefit of