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dts/riscv: remove the timebase-frequency property

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The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.

As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-01-19 08:55:34 +01:00 committed by Carles Cufí
parent c592690649
commit 17670be2cc
6 changed files with 0 additions and 6 deletions
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1
dts/riscv/andes/andes_v5_ae350.dtsi
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@ -15,7 +15,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <60000000>;
CPU0: cpu@0 {
compatible = "riscv";
device_type = "cpu";

1
dts/riscv/efinix/sapphire_soc.dtsi
View file

@ -32,7 +32,6 @@
reg = <0>;
riscv,isa = "rv32ima_zicsr_zifencei";
status = "okay";
timebase-frequency = <100000000>;
hlic: interrupt-controller {
compatible = "riscv,cpu-intc";

1
dts/riscv/lowrisc/opentitan_earlgrey.dtsi
View file

@ -12,7 +12,6 @@
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <10000000>;
cpu@0 {
device_type = "cpu";

1
dts/riscv/riscv32-litex-vexriscv.dtsi
View file

@ -25,7 +25,6 @@
reg = <0>;
riscv,isa = "rv32ima_zicsr_zifencei";
status = "okay";
timebase-frequency = <32768>;
};
};
soc {

1
dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
View file

@ -16,7 +16,6 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <6250000>;
compatible = "starfive,fu74-g000";
cpu@0 {
clock-frequency = <0>;

1
dts/riscv/virt.dtsi
View file

@ -36,7 +36,6 @@
cpus {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
timebase-frequency = < 10000000 >;
cpu@0 {
device_type = "cpu";