arch: arm: rename expection header
Rename exception header and use the same name as all architecture ports. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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@ -12,7 +12,7 @@
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#include <offsets_short.h>
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#include <zephyr/syscall.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
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#include <zephyr/arch/cpu.h>
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@ -23,7 +23,7 @@
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#else
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#include <cmsis_core.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#include <zephyr/irq_offload.h>
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#ifdef __cplusplus
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@ -262,7 +262,7 @@ interrupt. If the ZLI feature is enabled in Mainline Cortex-M builds (see
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* Regular HW interrupts are assigned priority levels lower than SVC.
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The priority level configuration in Cortex-M is implemented in
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:file:`include/arch/arm/exc.h`.
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:file:`include/arch/arm/exception.h`.
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Locking and unlocking IRQs
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--------------------------
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@ -23,7 +23,7 @@
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#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
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#include <zephyr/arch/arm/thread.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#include <zephyr/arch/arm/irq.h>
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#include <zephyr/arch/arm/error.h>
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#include <zephyr/arch/arm/misc.h>
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@ -20,7 +20,7 @@
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#include <zephyr/toolchain.h>
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#include <zephyr/types.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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#include <zephyr/arch/arm/cortex_a_r/cpu.h>
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@ -16,7 +16,7 @@
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ERROR_H_
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#include <zephyr/arch/arm/syscall.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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@ -8,7 +8,7 @@
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/sys/printk.h>
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#include <cmsis_core.h>
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#include <zephyr/arch/arm/exc.h>
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#include <zephyr/arch/arm/exception.h>
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#define LED0_NODE DT_ALIAS(led0)
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static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios);
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