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dts: arm: nuvoton: add I3C device nodes

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Add I3C device nodes.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
This commit is contained in:
Alvis Sun 2024-04-17 11:03:50 +08:00 committed by Fabio Baltieri
parent 3ed5f8a948
commit 18f6a541f2
1 changed files with 77 additions and 0 deletions
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77
dts/arm/nuvoton/npcx/npcx4.dtsi
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@ -14,6 +14,8 @@
#include "npcx4/npcx4-espi-vws-map.dtsi"
/* npcx4 series low-voltage io controls mapping table */
#include "npcx4/npcx4-lvol-ctrl-map.dtsi"
/* npcx4 series reset mapping table*/
#include "zephyr/dt-bindings/reset/npcx4_reset.h"
/* Device tree declarations of npcx soc family */
#include "npcx.dtsi"
@ -324,6 +326,81 @@
#reset-cells = <1>;
status = "disabled";
};
i3c0: i3c@400f0000 {
compatible = "nuvoton,npcx-i3c";
/* reg[0]: I3C_1 register, reg[1]: MDMA5 register */
reg-names = "i3c1", "mdma5";
reg = <0x400f0000 0x2000>,
<0x40011500 0x100>;
interrupts = <29 3>;
/* Reset controller */
resets = <&rctl NPCX_RESET_I3C_1>;
/* clk[0]: I3C source clock, clk[1]: timeout reference clock */
/* clk[2]: MDMA5 */
clock-names = "mclkd", "apb4", "mdma5";
clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 0>,
<&pcc NPCX_CLOCK_BUS_APB4 0 0>,
<&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 4>;
status = "disabled";
#address-cells = <3>;
#size-cells = <0>;
};
i3c1: i3c@400f2000 {
compatible = "nuvoton,npcx-i3c";
/* reg[0]: I3C_2 register, reg[1]: MDMA6 register */
reg-names = "i3c2", "mdma6";
reg = <0x400f2000 0x2000>,
<0x40011600 0x100>;
interrupts = <66 3>;
/* Reset controller */
resets = <&rctl NPCX_RESET_I3C_2>;
/* clk[0]: I3C source clock, clk[1]: timeout reference clock */
/* clk[2]: MDMA6 */
clock-names = "mclkd", "apb4", "mdma6";
clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 2>,
<&pcc NPCX_CLOCK_BUS_APB4 0 0>,
<&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 5>;
status = "disabled";
#address-cells = <3>;
#size-cells = <0>;
};
i3c2: i3c@400f4000 {
compatible = "nuvoton,npcx-i3c";
/* reg[0]: I3C_3 register, reg[1]: MDMA7 register */
reg-names = "i3c1", "mdma7";
reg = <0x400f4000 0x2000>,
<0x40011700 0x100>;
interrupts = <67 3>;
/* Reset controller */
resets = <&rctl NPCX_RESET_I3C_3>;
/* clk[0]: I3C source clock, clk[1]: timeout reference clock */
/* clk[2]: MDMA7 */
clock-names = "mclkd", "apb4", "mdma7";
clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 3>,
<&pcc NPCX_CLOCK_BUS_APB4 0 0>,
<&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 6>;
status = "disabled";
#address-cells = <3>;
#size-cells = <0>;
};
};
soc-if {