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boards, dts: fix namespace for intel adsp cavs, ace

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Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This commit is contained in:
Lauren Murphy 2022-08-10 14:39:08 -07:00 committed by Anas Nashif
parent ca5d698563
commit 1983a4c50c
23 changed files with 86 additions and 86 deletions
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2
boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs15.dtsi>
#include <intel/intel_adsp_cavs15.dtsi>
/ {
model = "intel_adsp_cavs15";

2
boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs18.dtsi>
#include <intel/intel_adsp_cavs18.dtsi>
/ {
model = "intel_adsp_cavs18";

2
boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs20.dtsi>
#include <intel/intel_adsp_cavs20.dtsi>
/ {
model = "intel_adsp_cavs20";

2
boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs20_jsl.dtsi>
#include <intel/intel_adsp_cavs20_jsl.dtsi>
/ {
model = "intel_adsp_cavs20_jsl";

2
boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs25.dtsi>
#include <intel/intel_adsp_cavs25.dtsi>
/ {
model = "intel_adsp_cavs25";

2
boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <intel/intel_cavs25_tgph.dtsi>
#include <intel/intel_adsp_cavs25_tgph.dtsi>
/ {
model = "intel_adsp_cavs25_tgph";

2
drivers/clock_control/CMakeLists.txt
View file

@ -3,7 +3,7 @@
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_CAVS clock_control_cavs.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_cavs.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)

6
drivers/clock_control/Kconfig.cavs
View file

@ -3,11 +3,11 @@
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Idertifier: Apache-2.0
config CLOCK_CONTROL_CAVS
config CLOCK_CONTROL_ADSP
bool "Intel CAVS clock control"
default y
depends on DT_HAS_INTEL_CAVS_SHIM_CLKCTL_ENABLED
select CAVS_CLOCK
depends on DT_HAS_INTEL_ADSP_SHIM_CLKCTL_ENABLED
select ADSP_CLOCK
help
Driver for the CAVS clocks. Allow type of clock (and
thus frequency) to be chosen.

2
drivers/ipm/ipm_cavs_idc.c
View file

@ -188,7 +188,7 @@ static int cavs_idc_set_enabled(const struct device *dev, int enable)
idc_write(IPC_IDCCTL, i, mask);
/* FIXME: when we have API to enable IRQ on specific core. */
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs_intc0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(i),
CAVS_IRQ_NUMBER(DT_INST_IRQN(0)));
}

2
dts/bindings/clock/intel,cavs-shim-clkctl.yaml → dts/bindings/clock/intel,adsp-shim-clkctl.yaml
View file

@ -3,7 +3,7 @@
description: Intel cAVS clock controlling related constants.
compatible: "intel,cavs-shim-clkctl"
compatible: "intel,adsp-shim-clkctl"
properties:
cavs-clkctl-clk-wovcro:

2
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -143,7 +143,7 @@
};
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};

4
dts/xtensa/intel/intel_cavs.dtsi → dts/xtensa/intel/intel_adsp_cavs.dtsi
View file

@ -14,7 +14,7 @@
reg = <0x0007c000 0x1000>;
shim = <0x00078400 0x100>;
interrupts = <0x10 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
status = "okay";
};
@ -25,7 +25,7 @@
reg = <0x0007d000 0x1000>;
shim = <0x00078500 0x100>;
interrupts = <0x0F 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
status = "okay";
};

32
dts/xtensa/intel/intel_cavs15.dtsi → dts/xtensa/intel/intel_adsp_cavs15.dtsi
View file

@ -54,7 +54,7 @@
};
clkctl: clkctl {
compatible = "intel,cavs-shim-clkctl";
compatible = "intel,adsp-shim-clkctl";
cavs-clkctl-clk-lpro = <0>;
cavs-clkctl-clk-hpro = <2>;
cavs-clkctl-freq-enc = <0x3 0x1 0x0>;
@ -64,7 +64,7 @@
soc {
shim: shim@1000 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x1000 0x100>;
};
@ -89,10 +89,10 @@
compatible = "intel,adsp-host-ipc";
reg = <0x1180 0x30>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
cavs0: cavs@1600 {
cavs_intc0: cavs@1600 {
compatible = "intel,cavs-intc";
reg = <0x1600 0x10>;
interrupt-controller;
@ -101,7 +101,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@1610 {
cavs_intc1: cavs@1610 {
compatible = "intel,cavs-intc";
reg = <0x1610 0x10>;
interrupt-controller;
@ -110,7 +110,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@1620 {
cavs_intc2: cavs@1620 {
compatible = "intel,cavs-intc";
reg = <0x1620 0x10>;
interrupt-controller;
@ -119,7 +119,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@1630 {
cavs_intc3: cavs@1630 {
compatible = "intel,cavs-intc";
reg = <0x1630 0x10>;
interrupt-controller;
@ -132,7 +132,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
lpgpdma0: dma@c000 {
@ -141,7 +141,7 @@
reg = <0x0000c000 0x1000>;
shim = <0x00000c00 0x080>;
interrupts = <0x10 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
status = "okay";
};
@ -152,7 +152,7 @@
reg = <0x0000d000 0x1000>;
shim = <0x00000c80 0x080>;
interrupts = <0x0F 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
status = "okay";
};
@ -204,7 +204,7 @@
reg = <0x00008000 0x200
0x00008E00 0x008>;
interrupts = <0x01 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 2
&lpgpdma0 3>;
dma-names = "tx", "rx";
@ -219,7 +219,7 @@
reg = <0x00008200 0x200
0x00008E00 0x008>;
interrupts = <0x01 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 4
&lpgpdma0 5>;
dma-names = "tx", "rx";
@ -234,7 +234,7 @@
reg = <0x00008400 0x200
0x00008E00 0x008>;
interrupts = <0x02 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 6
&lpgpdma0 7>;
dma-names = "tx", "rx";
@ -249,7 +249,7 @@
reg = <0x00008600 0x200
0x00008E00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 8
&lpgpdma0 9>;
dma-names = "tx", "rx";
@ -264,7 +264,7 @@
reg = <0x00008800 0x200
0x00008E00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 10
&lpgpdma0 11>;
dma-names = "tx", "rx";
@ -279,7 +279,7 @@
reg = <0x00008A00 0x200
0x00008E00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 12
&lpgpdma0 13>;
dma-names = "tx", "rx";

18
dts/xtensa/intel/intel_cavs18.dtsi → dts/xtensa/intel/intel_adsp_cavs18.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/intel/intel_cavs.dtsi>
#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>
/ {
@ -50,7 +50,7 @@
};
clkctl: clkctl {
compatible = "intel,cavs-shim-clkctl";
compatible = "intel,adsp-shim-clkctl";
cavs-clkctl-clk-lpro = <0>;
cavs-clkctl-clk-hpro = <1>;
cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
@ -61,7 +61,7 @@
soc {
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};
@ -86,10 +86,10 @@
compatible = "intel,adsp-host-ipc";
reg = <0x71e00 0x30>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
cavs0: cavs@78800 {
cavs_intc0: cavs@78800 {
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
@ -98,7 +98,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@78810 {
cavs_intc1: cavs@78810 {
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
@ -107,7 +107,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
cavs_intc2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
@ -116,7 +116,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
cavs_intc3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
@ -129,7 +129,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
};
};

18
dts/xtensa/intel/intel_cavs20.dtsi → dts/xtensa/intel/intel_adsp_cavs20.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/intel/intel_cavs.dtsi>
#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>
/ {
@ -50,7 +50,7 @@
};
clkctl: clkctl {
compatible = "intel,cavs-shim-clkctl";
compatible = "intel,adsp-shim-clkctl";
cavs-clkctl-clk-lpro = <0>;
cavs-clkctl-clk-hpro = <1>;
cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
@ -61,7 +61,7 @@
soc {
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};
@ -86,10 +86,10 @@
compatible = "intel,adsp-host-ipc";
reg = <0x71e00 0x30>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
cavs0: cavs@78800 {
cavs_intc0: cavs@78800 {
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
@ -98,7 +98,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@78810 {
cavs_intc1: cavs@78810 {
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
@ -107,7 +107,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
cavs_intc2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
@ -116,7 +116,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
cavs_intc3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
@ -129,7 +129,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
};

16
dts/xtensa/intel/intel_cavs20_jsl.dtsi → dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/intel/intel_cavs.dtsi>
#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>
/ {
@ -40,7 +40,7 @@
soc {
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};
@ -65,10 +65,10 @@
compatible = "intel,adsp-host-ipc";
reg = <0x71e00 0x30>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
cavs0: cavs@78800 {
cavs_intc0: cavs@78800 {
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
@ -77,7 +77,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@78810 {
cavs_intc1: cavs@78810 {
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
@ -86,7 +86,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
cavs_intc2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
@ -95,7 +95,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
cavs_intc3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
@ -108,7 +108,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
};

30
dts/xtensa/intel/intel_cavs25.dtsi → dts/xtensa/intel/intel_adsp_cavs25.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/intel/intel_cavs.dtsi>
#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>
/ {
@ -68,7 +68,7 @@
};
clkctl: clkctl {
compatible = "intel,cavs-shim-clkctl";
compatible = "intel,adsp-shim-clkctl";
cavs-clkctl-clk-wovcro = <0>;
cavs-clkctl-clk-lpro = <1>;
cavs-clkctl-clk-hpro = <2>;
@ -81,7 +81,7 @@
soc {
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};
@ -111,10 +111,10 @@
compatible = "intel,adsp-host-ipc";
reg = <0x71e00 0x30>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
cavs0: cavs@78800 {
cavs_intc0: cavs@78800 {
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
@ -123,7 +123,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@78810 {
cavs_intc1: cavs@78810 {
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
@ -132,7 +132,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
cavs_intc2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
@ -141,7 +141,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
cavs_intc3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
@ -154,7 +154,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
tlb: tlb@3000 {
@ -170,7 +170,7 @@
reg = <0x00077000 0x200
0x00078C00 0x008>;
interrupts = <0x01 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 2
&lpgpdma0 3>;
dma-names = "tx", "rx";
@ -185,7 +185,7 @@
reg = <0x00077200 0x200
0x00078C00 0x008>;
interrupts = <0x01 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 4
&lpgpdma0 5>;
dma-names = "tx", "rx";
@ -200,7 +200,7 @@
reg = <0x00077400 0x200
0x00078C00 0x008>;
interrupts = <0x02 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 6
&lpgpdma0 7>;
dma-names = "tx", "rx";
@ -215,7 +215,7 @@
reg = <0x00077600 0x200
0x00078C00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 8
&lpgpdma0 9>;
dma-names = "tx", "rx";
@ -230,7 +230,7 @@
reg = <0x00077800 0x200
0x00078C00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 10
&lpgpdma0 11>;
dma-names = "tx", "rx";
@ -245,7 +245,7 @@
reg = <0x00077A00 0x200
0x00078C00 0x008>;
interrupts = <0x03 0 0>;
interrupt-parent = <&cavs3>;
interrupt-parent = <&cavs_intc3>;
dmas = <&lpgpdma0 12
&lpgpdma0 13>;
dma-names = "tx", "rx";

14
dts/xtensa/intel/intel_cavs25_tgph.dtsi → dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/intel/intel_cavs.dtsi>
#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>
/ {
@ -39,7 +39,7 @@
soc {
shim: shim@71f00 {
compatible = "intel,cavs-shim";
compatible = "intel,adsp-shim";
reg = <0x71f00 0x100>;
};
@ -60,7 +60,7 @@
#interrupt-cells = <3>;
};
cavs0: cavs@78800 {
cavs_intc0: cavs@78800 {
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
@ -69,7 +69,7 @@
interrupt-parent = <&core_intc>;
};
cavs1: cavs@78810 {
cavs_intc1: cavs@78810 {
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
@ -78,7 +78,7 @@
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
cavs_intc2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
@ -87,7 +87,7 @@
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
cavs_intc3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
@ -100,7 +100,7 @@
compatible = "intel,adsp-idc";
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
interrupt-parent = <&cavs_intc0>;
};
tlb: tlb@3000 {

6
include/zephyr/drivers/clock_control/clock_control_cavs.h
View file

@ -3,9 +3,9 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef CLOCK_CONTROL_CAVS_H_
#define CLOCK_CONTROL_CAVS_H_
#ifndef CLOCK_CONTROL_ADSP_H_
#define CLOCK_CONTROL_ADSP_H_
#include <cavs-clk.h>
#endif /* CLOCK_CONTROL_CAVS_H_ */
#endif /* CLOCK_CONTROL_ADSP_H_ */

2
soc/xtensa/intel_adsp/Kconfig
View file

@ -28,7 +28,7 @@ config INTEL_ADSP_IPC
Driver for the host IPC interrupt delivery mechanism.
Currently SOF has its own driver for this hardware.
config CAVS_CLOCK
config ADSP_CLOCK
bool
help
Driver for the CAVS clocks. Allow type of clock (and

2
soc/xtensa/intel_adsp/common/CMakeLists.txt
View file

@ -18,7 +18,7 @@ zephyr_library_sources(
soc.c
)
zephyr_library_sources_ifdef(CONFIG_CAVS_CLOCK clk.c)
zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c)
if(CONFIG_SMP OR CONFIG_MP_NUM_CPUS GREATER 1)
zephyr_library_sources(multiprocessing.c)

2
soc/xtensa/intel_adsp/common/include/cavs-idc.h
View file

@ -145,6 +145,6 @@ struct cavs_intctrl {
#define CAVS_L5_I2S(n) BIT(n) /* I2S */
#define CAVS_INTCTRL \
((volatile struct cavs_intctrl *)DT_REG_ADDR(DT_NODELABEL(cavs0)))
((volatile struct cavs_intctrl *)DT_REG_ADDR(DT_NODELABEL(cavs_intc0)))
#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_ */

2
soc/xtensa/intel_adsp/common/soc.c
View file

@ -16,7 +16,7 @@ static __imr int soc_init(const struct device *dev)
{
power_init();
#ifdef CONFIG_CAVS_CLOCK
#ifdef CONFIG_ADSP_CLOCK
cavs_clock_init();
#endif