diff --git a/drivers/clock_control/clock_control_adsp.c b/drivers/clock_control/clock_control_adsp.c
index b9f10516d6..adcab94b9a 100644
--- a/drivers/clock_control/clock_control_adsp.c
+++ b/drivers/clock_control/clock_control_adsp.c
@@ -13,7 +13,7 @@ static int cavs_clock_ctrl_set_rate(const struct device *clk,
 {
 	uint32_t freq_idx = (uint32_t)rate;
 
-	return adsp_clock_set_freq(freq_idx);
+	return adsp_clock_set_cpu_freq(freq_idx);
 }
 
 static int cavs_clock_ctrl_init(const struct device *dev)
diff --git a/soc/xtensa/intel_adsp/common/clk.c b/soc/xtensa/intel_adsp/common/clk.c
index 4bf76af274..679e04a16c 100644
--- a/soc/xtensa/intel_adsp/common/clk.c
+++ b/soc/xtensa/intel_adsp/common/clk.c
@@ -13,11 +13,11 @@
 #include <adsp_clk.h>
 #include <adsp_shim.h>
 
-static struct adsp_clock_info platform_clocks[CONFIG_MP_MAX_NUM_CPUS];
+static struct adsp_cpu_clock_info platform_cpu_clocks[CONFIG_MP_MAX_NUM_CPUS];
 static struct k_spinlock lock;
 
-int adsp_clock_freq_enc[] = ADSP_CLOCK_FREQ_ENC;
-int adsp_clock_freq_mask[] = ADSP_CLOCK_FREQ_MASK;
+int adsp_clock_freq_enc[] = ADSP_CPU_CLOCK_FREQ_ENC;
+int adsp_clock_freq_mask[] = ADSP_CPU_CLOCK_FREQ_MASK;
 
 static void select_cpu_clock_hw(uint32_t freq_idx)
 {
@@ -40,12 +40,12 @@ static void select_cpu_clock_hw(uint32_t freq_idx)
 	ADSP_CLKCTL &= ~ADSP_CLKCTL_OSC_REQUEST_MASK | enc;
 }
 
-int adsp_clock_set_freq(uint32_t freq_idx)
+int adsp_clock_set_cpu_freq(uint32_t freq_idx)
 {
 	k_spinlock_key_t k;
 	int i;
 
-	if (freq_idx >= ADSP_CLOCK_FREQ_LEN) {
+	if (freq_idx >= ADSP_CPU_CLOCK_FREQ_LEN) {
 		return -EINVAL;
 	}
 
@@ -56,7 +56,7 @@ int adsp_clock_set_freq(uint32_t freq_idx)
 	unsigned int num_cpus = arch_num_cpus();
 
 	for (i = 0; i < num_cpus; i++) {
-		platform_clocks[i].current_freq = freq_idx;
+		platform_cpu_clocks[i].current_freq = freq_idx;
 	}
 
 	k_spin_unlock(&lock, k);
@@ -64,14 +64,14 @@ int adsp_clock_set_freq(uint32_t freq_idx)
 	return 0;
 }
 
-struct adsp_clock_info *adsp_clocks_get(void)
+struct adsp_cpu_clock_info *adsp_cpu_clocks_get(void)
 {
-	return platform_clocks;
+	return platform_cpu_clocks;
 }
 
 void adsp_clock_init(void)
 {
-	uint32_t platform_lowest_freq_idx = ADSP_CLOCK_FREQ_LOWEST;
+	uint32_t platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LOWEST;
 	int i;
 
 #ifdef ADSP_CLOCK_HAS_WOVCRO
@@ -80,14 +80,14 @@ void adsp_clock_init(void)
 	if (ACE_DfPMCCU.dfclkctl & ACE_CLKCTL_WOVCRO) {
 		ACE_DfPMCCU.dfclkctl = ACE_DfPMCCU.dfclkctl & ~ACE_CLKCTL_WOVCRO;
 	} else {
-		platform_lowest_freq_idx = ADSP_CLOCK_FREQ_LPRO;
+		platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LPRO;
 	}
 #else
 	CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO;
 	if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO) {
 		CAVS_SHIM.clkctl = CAVS_SHIM.clkctl & ~CAVS_CLKCTL_WOVCRO;
 	} else {
-		platform_lowest_freq_idx = ADSP_CLOCK_FREQ_LPRO;
+		platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LPRO;
 	}
 #endif /* CONFIG_SOC_SERIES_INTEL_ACE */
 #endif /* ADSP_CLOCK_HAS_WOVCRO */
@@ -95,8 +95,8 @@ void adsp_clock_init(void)
 	unsigned int num_cpus = arch_num_cpus();
 
 	for (i = 0; i < num_cpus; i++) {
-		platform_clocks[i].default_freq = ADSP_CLOCK_FREQ_DEFAULT;
-		platform_clocks[i].current_freq = ADSP_CLOCK_FREQ_DEFAULT;
-		platform_clocks[i].lowest_freq = platform_lowest_freq_idx;
+		platform_cpu_clocks[i].default_freq = ADSP_CPU_CLOCK_FREQ_DEFAULT;
+		platform_cpu_clocks[i].current_freq = ADSP_CPU_CLOCK_FREQ_DEFAULT;
+		platform_cpu_clocks[i].lowest_freq = platform_lowest_freq_idx;
 	}
 }
diff --git a/soc/xtensa/intel_adsp/common/include/adsp_clk.h b/soc/xtensa/intel_adsp/common/include/adsp_clk.h
index 166a0b994b..c2c7fa2d54 100644
--- a/soc/xtensa/intel_adsp/common/include/adsp_clk.h
+++ b/soc/xtensa/intel_adsp/common/include/adsp_clk.h
@@ -9,7 +9,7 @@
 #include <stdint.h>
 #include <adsp_shim.h>
 
-struct adsp_clock_info {
+struct adsp_cpu_clock_info {
 	uint32_t default_freq;
 	uint32_t current_freq;
 	uint32_t lowest_freq;
@@ -25,7 +25,7 @@ void adsp_clock_init(void);
  *
  * @return 0 on success, -EINVAL if freq_idx is not valid
  */
-int adsp_clock_set_freq(uint32_t freq_idx);
+int adsp_clock_set_cpu_freq(uint32_t freq_idx);
 
 /** @brief Get list of cAVS clock information
  *
@@ -33,7 +33,7 @@ int adsp_clock_set_freq(uint32_t freq_idx);
  *
  * @return array with clock information
  */
-struct adsp_clock_info *adsp_clocks_get(void);
+struct adsp_cpu_clock_info *adsp_cpu_clocks_get(void);
 
 /* Device tree defined constants */
 #ifdef CONFIG_SOC_SERIES_INTEL_ACE
@@ -42,23 +42,23 @@ struct adsp_clock_info *adsp_clocks_get(void);
 #define ADSP_CLKCTL		CAVS_SHIM.clkctl
 #endif
 
-#define ADSP_CLOCK_FREQ_ENC     DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
-#define ADSP_CLOCK_FREQ_MASK    DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_mask)
-#define ADSP_CLOCK_FREQ_LEN     DT_PROP_LEN(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
+#define ADSP_CPU_CLOCK_FREQ_ENC     DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
+#define ADSP_CPU_CLOCK_FREQ_MASK    DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_mask)
+#define ADSP_CPU_CLOCK_FREQ_LEN     DT_PROP_LEN(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
 
-#define ADSP_CLOCK_FREQ_DEFAULT DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_default)
-#define ADSP_CLOCK_FREQ_LOWEST  DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_lowest)
+#define ADSP_CPU_CLOCK_FREQ_DEFAULT DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_default)
+#define ADSP_CPU_CLOCK_FREQ_LOWEST  DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_lowest)
 
-#define ADSP_CLOCK_FREQ(name)   DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_clk_##name)
+#define ADSP_CPU_CLOCK_FREQ(name)   DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_clk_##name)
 
 #if DT_PROP(DT_NODELABEL(clkctl), wovcro_supported)
 #define ADSP_CLOCK_HAS_WOVCRO
 #endif
 
-#define ADSP_CLOCK_FREQ_LPRO  ADSP_CLOCK_FREQ(lpro)
-#define ADSP_CLOCK_FREQ_HPRO  ADSP_CLOCK_FREQ(hpro)
+#define ADSP_CPU_CLOCK_FREQ_LPRO  ADSP_CPU_CLOCK_FREQ(lpro)
+#define ADSP_CPU_CLOCK_FREQ_HPRO  ADSP_CPU_CLOCK_FREQ(hpro)
 #ifdef ADSP_CLOCK_HAS_WOVCRO
-#define ADSP_CLOCK_FREQ_WOVCRO  ADSP_CLOCK_FREQ(wovcro)
+#define ADSP_CPU_CLOCK_FREQ_WOVCRO  ADSP_CPU_CLOCK_FREQ(wovcro)
 #endif
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_CLK_H_ */
diff --git a/tests/drivers/clock_control/adsp_clock/src/main.c b/tests/drivers/clock_control/adsp_clock/src/main.c
index f4977c1d4f..c4af442d2a 100644
--- a/tests/drivers/clock_control/adsp_clock/src/main.c
+++ b/tests/drivers/clock_control/adsp_clock/src/main.c
@@ -7,7 +7,7 @@
 #include <zephyr/drivers/clock_control/clock_control_adsp.h>
 #include <zephyr/drivers/clock_control.h>
 
-static void check_clocks(struct adsp_clock_info *clocks, uint32_t freq_idx)
+static void check_clocks(struct adsp_cpu_clock_info *clocks, uint32_t freq_idx)
 {
 	int i;
 	unsigned int num_cpus = arch_num_cpus();
@@ -19,41 +19,41 @@ static void check_clocks(struct adsp_clock_info *clocks, uint32_t freq_idx)
 
 ZTEST(adsp_clock_control, test_adsp_clock_driver)
 {
-	struct adsp_clock_info *clocks = adsp_clocks_get();
+	struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get();
 
 	zassert_not_null(clocks, "");
 
-	adsp_clock_set_freq(ADSP_CLOCK_FREQ_LPRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_LPRO);
+	adsp_clock_set_cpu_freq(ADSP_CPU_CLOCK_FREQ_LPRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO);
 
-	adsp_clock_set_freq(ADSP_CLOCK_FREQ_HPRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_HPRO);
+	adsp_clock_set_cpu_freq(ADSP_CPU_CLOCK_FREQ_HPRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO);
 
 #ifdef ADSP_CLOCK_HAS_WOVCRO
-	adsp_clock_set_freq(ADSP_CLOCK_FREQ_WOVCRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_WOVCRO);
+	adsp_clock_set_cpu_freq(ADSP_CPU_CLOCK_FREQ_WOVCRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO);
 #endif
 }
 
 ZTEST(adsp_clock_control, test_adsp_clock_control)
 {
-	struct adsp_clock_info *clocks = adsp_clocks_get();
+	struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get();
 	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(clkctl));
 
 	zassert_not_null(clocks, "");
 
 	clock_control_set_rate(dev, NULL, (clock_control_subsys_rate_t)
-					   ADSP_CLOCK_FREQ_LPRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_LPRO);
+					   ADSP_CPU_CLOCK_FREQ_LPRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO);
 
 	clock_control_set_rate(dev, NULL, (clock_control_subsys_rate_t)
-					   ADSP_CLOCK_FREQ_HPRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_HPRO);
+					   ADSP_CPU_CLOCK_FREQ_HPRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO);
 
 #ifdef ADSP_CLOCK_HAS_WOVCRO
 	clock_control_set_rate(dev, NULL, (clock_control_subsys_rate_t)
-					   ADSP_CLOCK_FREQ_WOVCRO);
-	check_clocks(clocks, ADSP_CLOCK_FREQ_WOVCRO);
+					   ADSP_CPU_CLOCK_FREQ_WOVCRO);
+	check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO);
 #endif
 }
 ZTEST_SUITE(adsp_clock_control, NULL, NULL, NULL, NULL, NULL);