boards: risc-v: add BeagleV Starlight JH7100 board support

Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>

CODEOWNERS

@@ -143,6 +143,7 @@
 /boards/posix/nrf52_bsim/                 @aescolar @wopu-ot
 /boards/riscv/                            @kgugala @pgielda
 /boards/riscv/rv32m1_vega/                @MaureenHelm
+/boards/riscv/beaglev_starlight_jh7100/   @rajnesh-kanwal
 /boards/shields/                          @erwango
 /boards/shields/atmel_rf2xx/              @nandojve
 /boards/shields/esp_8266/                 @nandojve
@@ -377,6 +378,7 @@
 /dts/riscv/microsemi-miv.dtsi             @galak
 /dts/riscv/rv32m1*                        @MaureenHelm
 /dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
+/dts/riscv/starfive/                      @rajnesh-kanwal
 /dts/arm/armv*m.dtsi                      @galak @ioannisg
 /dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
 /dts/arm/xilinx/                          @bbolen @stephanosio

boards/riscv/beaglev_starlight_jh7100/Kconfig.board

@@ -0,0 +1,7 @@
+# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BEAGLEV_STARLIGHT_JH7100
+	bool "BeagleV Starlight JH7100 RISCV64 target"
+	depends on SOC_JH7100
+	select 64BIT

boards/riscv/beaglev_starlight_jh7100/Kconfig.defconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD
+	default "beaglev_starlight_jh7100"
+	depends on BOARD_BEAGLEV_STARLIGHT_JH7100

boards/riscv/beaglev_starlight_jh7100/beaglev_starlight_jh7100.dts

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "starfive/starfive_jh7100_beagle_v.dtsi"
+
+/ {
+	model = "BeagleV StarLight JH7100";
+	compatible = "beagle,beaglev-starlight-jh7100";
+
+	chosen {
+		zephyr,console = &uart3;
+		zephyr,shell-uart = &uart3;
+		zephyr,sram = &ram0;
+	};
+};
+
+&uart3 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/riscv/beaglev_starlight_jh7100/beaglev_starlight_jh7100.yaml

@@ -0,0 +1,9 @@
+identifier: beaglev_starlight_jh7100
+name: BeagleV Starlight JH7100 (NON-SMP)
+type: mcu
+arch: riscv64
+toolchain:
+  - zephyr
+  - cross-compile
+supported:
+  - uart

boards/riscv/beaglev_starlight_jh7100/beaglev_starlight_jh7100_defconfig

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_STARFIVE_JH71XX=y
+CONFIG_SOC_JH7100=y
+CONFIG_BOARD_BEAGLEV_STARLIGHT_JH7100=y
+CONFIG_PLIC=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_STACK_SENTINEL=y
+
+# Zephyr Kernel Configuration
+CONFIG_PRINTK=y
+CONFIG_XIP=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/riscv/beaglev_starlight_jh7100/board.cmake

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/riscv/beaglev_starlight_jh7100/doc/index.rst

@@ -0,0 +1,75 @@
+.. _beaglev_starlight_jh7100:
+
+BeagleV Starlight JH7100
+########################
+
+Overview
+********
+
+The BeagleV Starlight is an 64-bit open-source RISC-V development board with
+a StarFive JH7100 SoC.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``beaglev_starlight_jh7100`` board configuration can be built
+as usual (see :ref:`build_an_application`) using the corresponding board name:
+
+.. zephyr-app-commands::
+   :board: beaglev_starlight_jh7100
+   :goals: build
+
+The bootloader expects size information at the start of the binary file,
+so the bin file needs to be processed first to include that information.
+Download the helper script from starfive-tech github repo `here
+<https://github.com/starfive-tech/freelight-u-sdk/blob/starfive/fsz.sh>`_
+
+.. code-block:: console
+
+   ./fsz.sh build/zephyr/zephyr.bin
+
+This will create a new file build/zephyr/zephyr.bin.out that can be flashed.
+
+Flashing
+========
+
+.. note::
+   The following steps use minicom for serial communication, feel free to use
+   any other serial terminal that supports xmodem based file transfers.
+
+#. BeagleV Starlight uses uart for flashing. Refer to `BeagleV Getting Started
+   <https://wiki.seeedstudio.com/BeagleV-Getting-Started/>`_
+   to connect your serial-to-usb converter. Now power on the board and using
+   minicom access board's serial.
+
+   .. code-block:: console
+
+      minicom -D /dev/ttyUSB0 -b 115200
+
+#. Press any key to stop the boot sequence. This will output a menu
+
+   .. code-block:: console
+
+      ***************************************************
+      *************** FLASH PROGRAMMING *****************
+      ***************************************************
+
+      0:update uboot
+      1:quit
+      select the function:
+
+#. Select 0 to flash a new image.
+#. Press Ctrl+A and then press s to enter upload mode
+#. Select xmodem and press Enter
+#. Select Goto from the bottom tab menu and press Enter
+#. Enter the directory path and press Enter
+#. Select zephyr.bin.out by navigating using arrow keys, press Space and press Enter
+#. Once uploaded hit any key to continue and reset the board to boot the zephyr binary
+
+References
+==========
+
+`Update bootloader, ddr init boot, u-boot and Recover bootloader <https://wiki.seeedstudio.com/BeagleV-Update-bootloader-ddr-init-boot-uboot-Recover-bootloader/>`_

dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi

@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2021 StarFive, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "starfive_jh7100_clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,freedom-u74-arty";
+	model = "sifive,freedom-u74-arty";
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <6250000>;
+		compatible = "starfive,fu74-g000";
+		cpu@0 {
+			clock-frequency = <0>;
+			compatible = "starfive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			reg = <0>;
+			riscv,isa = "rv64imafdc";
+			starfive,itim = <&itim0>;
+			status = "okay";
+			tlb-split;
+			cpu0intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu@1 {
+			clock-frequency = <0>;
+			compatible = "starfive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			starfive,itim = <&itim1>;
+			status = "okay";
+			tlb-split;
+			cpu1intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	ram0:memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x0>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		#clock-cells = <1>;
+		compatible = "starfive,freedom-u74-arty", "simple-bus";
+		ranges;
+
+		cachectrl: cache-controller@2010000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
+			interrupt-parent = <&plic>;
+			interrupts = <128 1>, <131 1>, <129 1>, <130 1>;
+			/*next-level-cache = <&L40 &L36>;*/
+			reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
+			reg-names = "control", "sideband";
+		};
+
+		itim0: itim@1808000 {
+			compatible = "starfive,itim0";
+			reg = <0x0 0x1808000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+
+		itim1: itim@1820000 {
+			compatible = "starfive,itim0";
+			reg = <0x0 0x1820000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+
+		clint: clint@2000000 {
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			compatible = "riscv,clint0";
+			interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
+					       &cpu1intctrl 3 &cpu1intctrl 7 >;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			reg-names = "control";
+		};
+
+		plic: plic@c000000 {
+			#interrupt-cells = <2>;
+			compatible = "sifive,plic-1.0.0";
+			interrupt-controller;
+			interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9
+					       &cpu1intctrl 11 &cpu1intctrl 9 >;
+			reg = <0x0 0x0c000000 0x0 0x00002000
+			       0x0 0x0c002000 0x0 0x001fe000
+			       0x0 0x0c200000 0x0 0x03e00000>;
+			reg-names = "prio", "irq_en", "reg";
+			riscv,max-priority = <7>;
+			riscv,ndev = <127>;
+		};
+
+		uart3: serial@12440000 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			interrupt-parent = <&plic>;
+			interrupts = <73 1>;
+			label = "UART_3";
+			reg = <0x0 0x12440000 0x0 0x10000>;
+			reg-shift = <2>;
+			clocks = <&uartclk>, <&apb2clk>;
+			clock-names = "baudclk", "apb_pclk";
+			clock-frequency = <100000000>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart2: serial@12430000 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			interrupt-parent = <&plic>;
+			interrupts = <72 1>;
+			label = "UART_2";
+			reg = <0x0 0x12430000 0x0 0x10000>;
+			reg-shift = <2>;
+			clocks = <&uartclk>, <&apb2clk>;
+			clock-names = "baudclk", "apb_pclk";
+			clock-frequency = <100000000>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart1: hs_serial@11880000 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			interrupt-parent = <&plic>;
+			interrupts = <93 1>;
+			label = "UART_1";
+			reg = <0x0 0x11880000 0x0 0x10000>;
+			reg-shift = <2>;
+			clocks = <&hs_uartclk>, <&apb1clk>;
+			clock-names = "baudclk","apb_pclk";
+			clock-frequency = <74250000>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart0: hs_serial@11870000 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			interrupt-parent = <&plic>;
+			interrupts = <92 1>;
+			label = "UART_0";
+			reg = <0x0 0x11870000 0x0 0x10000>;
+			reg-shift = <2>;
+			clocks = <&hs_uartclk>, <&apb1clk>;
+			clock-names = "baudclk", "apb_pclk";
+			clock-frequency = <74250000>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+	};
+};

dts/riscv/starfive/starfive_jh7100_clk.dtsi

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2021 StarFive, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	apb1clk: apb1clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+	};
+
+	apb2clk: apb2clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+	};
+
+	uartclk: uartclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
+
+	hs_uartclk: hs_uartclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <74250000>;
+	};
+};

soc/riscv/riscv-privilege/starfive_jh71xx/CMakeLists.txt

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series

@@ -0,0 +1,30 @@
+# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STARFIVE_JH71XX
+
+config SOC_SERIES
+	default "starfive_jh71xx"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 6250000
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+config RISCV_HAS_CPU_IDLE
+	default y
+
+config RISCV_HAS_PLIC
+	default y
+
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 12
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
+config NUM_IRQS
+	default 139
+
+endif

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.series

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STARFIVE_JH71XX
+	bool "Starfive JH71XX series"
+	select RISCV
+	select SOC_FAMILY_RISCV_PRIVILEGE
+	help
+	  Enable support for Starfive JH71XX SoC Series.

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.soc

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Starfive JH7100 SoC"
+	depends on SOC_SERIES_STARFIVE_JH71XX
+
+config SOC_JH7100
+	bool "Starfive JH7100"
+	select ATOMIC_OPERATIONS_BUILTIN
+
+endchoice

soc/riscv/riscv-privilege/starfive_jh71xx/linker.ld

@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2020 Cobham Gaisler AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <arch/riscv/common/linker.ld>

soc/riscv/riscv-privilege/starfive_jh71xx/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020 Cobham Gaisler AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV_VIRT_SOC_H_
+#define __RISCV_VIRT_SOC_H_
+
+#include <soc_common.h>
+#include <devicetree.h>
+
+#define RISCV_MTIME_BASE 0x0200BFF8
+#define RISCV_MTIMECMP_BASE 0x02004000
+
+#endif