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drivers: pinctrl: Enable pinctrl for RT11xx series

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RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-03-18 10:58:12 -05:00 committed by David Leach
parent 3a6919e3aa
commit 1cee7be552
9 changed files with 407 additions and 99 deletions
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4
drivers/pinctrl/Kconfig.mcux
View file

@ -2,10 +2,12 @@
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl
DT_COMPAT_MCUX_RT11XX_PINCTRL := nxp,mcux-rt11xx-pinctrl
config PINCTRL_MCUX_RT
bool "Pin controller driver for MCUX RT1xxx MCUs"
depends on SOC_SERIES_IMX_RT
default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL))
default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL)) || \
$(dt_compat_enabled,$(DT_COMPAT_MCUX_RT11XX_PINCTRL))
help
Enable pin controller driver for NXP RT series MCUs

13
drivers/pinctrl/pinctrl_mcux_rt.c
View file

@ -38,10 +38,11 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
input_daisy, config_register,
MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
input_daisy, config_register,
pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
if (config_register) {
IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
input_daisy, config_register,
pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
}
}
@ -53,8 +54,12 @@ static int mcux_pinctrl_init(const struct device *dev)
ARG_UNUSED(dev);
CLOCK_EnableClock(kCLOCK_Iomuxc);
#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
CLOCK_EnableClock(kCLOCK_IomuxcGpr);
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
#endif
return 0;
}

2
dts/arm/nxp/nxp_rt11xx.dtsi
View file

@ -350,7 +350,7 @@
status = "okay";
pinctrl: pinctrl {
status = "okay";
compatible = "nxp,mcux-rt-pinctrl";
compatible = "nxp,mcux-rt11xx-pinctrl";
};
};

37
dts/bindings/pinctrl/nxp,imx-iomuxc.yaml
View file

@ -44,3 +44,40 @@ child-binding:
gpr_reg: GPR register address to write to
gpr_shift: shift to apply to value before writing
gpr_val: value to write
# Note: the below properties should ideally be an enum. However, the pinctrl driver
# will need to initialize the pin configuration register differently based on
# the type of register provided, and it does so using the IF_ENABLED macro. This
# macro cannot work using preprocessor equality statements (like DT_ENUM_IDX(prop) == val),
# so we cannot use an enum and instead must use individual properties.
pin-pue:
required: false
type: boolean
description: |
RT11xx parts have multiple types of IOMUXC registers defined, with
different register layouts. This property can be set to indicate
to the pinctrl driver the type of register this pinmux represents,
and should not be modified by the user.
pin-pdrv:
required: false
type: boolean
description: |
RT11xx parts have multiple types of IOMUXC registers defined, with
different register layouts. This property can be set to indicate
to the pinctrl driver the type of register this pinmux represents,
and should not be modified by the user.
pin-lpsr:
required: false
type: boolean
description: |
RT11xx parts have multiple types of IOMUXC registers defined, with
different register layouts. This property can be set to indicate
to the pinctrl driver the type of register this pinmux represents,
and should not be modified by the user.
pin-snvs:
required: false
type: boolean
description: |
RT11xx parts have multiple types of IOMUXC registers defined, with
different register layouts. This property can be set to indicate
to the pinctrl driver the type of register this pinmux represents,
and should not be modified by the user.

2
dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml
View file

@ -17,8 +17,6 @@ description: |
nxp,speed = "100-mhz";
};
Note that the mux, mode, input, daisy, and cfg values must be aligned for
correct configuration
This will select GPIO_AD_B0_12 as LPUART1 TX, and GPIO_AD_B0_13 as LPUART1 RX.
Both pins will be configured with a weak latch, drive strength of "r0-6",
slow slew rate, and 100 MHZ speed.

92
dts/bindings/pinctrl/nxp,mcux-rt11xx-pinctrl.yaml Normal file
View file

@ -0,0 +1,92 @@
# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0
description: |
The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
nodes can be autogenerated using the MCUXpresso config tools combined with
the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
fields in a group select the pins to be configured, and the remaining
devicetree properties set configuration values for those pins
for example, here is an group configuring LPUART1 pins:
group0 {
pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
<&iomuxc_gpio_ad_24_lpuart1_txd>;
drive-strength = "high";
slew-rate = "slow";
};
This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
Both pins will be configured with a weak latch, high drive strength,
and slow slew rates.
Note that the soc level iomuxc dts file can be examined to find the possible
pinmux options. Here are the affects of each property on the
IOMUXC SW_PAD_CTL register:
drive-open-drain: ODE/ODE_LPSR=1
input-enable: SION=1 (in SW_MUX_CTL_PAD register)
bias-pull-down: PUE=1, PUS=0
bias-pull-up: PUE=1, PUS=1
bias-disable: PULL=11 (in supported registers)
slew-rate: SRE=<enum_idx>
drive-strength: DSE=<enum_idx>
If only required properties are supplied, the pin will have the following
configuration:
ODE=0
SION=0
PUE=0
PUS=0
SRE=0
DSE=0
For registers with PDVR and PULL fields, these are the defaults:
PULL=11
PDRV=0
compatible: "nxp,mcux-rt11xx-pinctrl"
include:
- name: base.yaml
- name: pincfg-node-group.yaml
child-binding:
child-binding:
property-allowlist:
- drive-open-drain
- input-enable
- bias-disable
- bias-pull-down
- bias-pull-up
child-binding:
description: MCUX RT pin controller pin group
child-binding:
description: |
MCUX RT pin controller pin configuration node.
properties:
pinmux:
required: true
type: phandles
description: |
Pin mux selections for this group. See the soc level iomuxc DTSI file
for a defined list of these options.
drive-strength:
required: false
type: string
enum:
- "normal"
- "high"
description: |
Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
0 (normal) - sets pin to normal drive strength
1 (high) - sets pin to high drive strength
slew-rate:
required: false
type: string
enum:
- "fast"
- "slow"
description: |
Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
0 (fast) — Fast Slew Rate
1 (slow) — Slow Slew Rate

100
soc/arm/nxp_imx/rt/pinctrl_rt10xx.h Normal file
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@ -0,0 +1,100 @@
/*
* Copyright (c) 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT10XX_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT10XX_H_
#include <devicetree.h>
#include <zephyr/types.h>
#include "fsl_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
#define MCUX_RT_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
#define MCUX_RT_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
#define MCUX_RT_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
#define MCUX_RT_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT
#define MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
#define MCUX_RT_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT
#define MCUX_RT_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#define MCUX_RT_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT
#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) | \
IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
<< MCUX_RT_BIAS_PULL_UP_SHIFT) |) \
IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
<< MCUX_RT_BIAS_PULL_DOWN_SHIFT) |) \
((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
<< MCUX_RT_BIAS_BUS_HOLD_SHIFT) | \
((!DT_PROP(node_id, bias_disable)) << MCUX_RT_PULL_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_ENUM_IDX(node_id, nxp_speed) << MCUX_RT_SPEED_SHIFT) | \
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_RT_DRIVE_STRENGTH_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_RT_SLEW_RATE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT))
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
uint32_t gpr_register; /* IOMUXC GPR register */
uint8_t gpr_shift: 5; /* bitshift for GPR register write */
uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
uint8_t gpr_val: 1; /* value to write to GPR register */
};
struct pinctrl_soc_pin {
struct pinctrl_soc_pinmux pinmux;
uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
};
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define MCUX_RT_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 0), \
(.gpr_register = DT_PROP_BY_IDX(node_id, gpr, 0),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 1), \
(.gpr_shift = DT_PROP_BY_IDX(node_id, gpr, 1),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 2), \
(.gpr_val = DT_PROP_BY_IDX(node_id, gpr, 2),)) \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(group_id), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT10XX_H_ */

161
soc/arm/nxp_imx/rt/pinctrl_rt11xx.h Normal file
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@ -0,0 +1,161 @@
/*
* Copyright (c) 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_
#include <devicetree.h>
#include <zephyr/types.h>
#include "fsl_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MCUX_RT_ODE_SHIFT 4
#define MCUX_RT_PUS_SHIFT 3
#define MCUX_RT_PUE_SHIFT 2
#define MCUX_RT_DSE_SHIFT 1
#define MCUX_RT_SRE_SHIFT 0
#define MCUX_RT_PULL_SHIFT 2
#define MCUX_RT_PULL_PULLDOWN 0x2
#define MCUX_RT_PULL_PULLUP 0x1
#define MCUX_RT_PDRV_SHIFT 1
#define MCUX_RT_LPSR_ODE_SHIFT 5
#define MCUX_RT_SNVS_ODE_SHIFT 6
#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
/*
* RT11xx has multiple types of register layouts defined for pin configuration
* registers. There are four types defined:
* pdrv_pull: registers lack a slew rate and pus field
* pue_pus: registers have a slew rate and ode field
* pue_pus_lpsr: in low power state retention domain, shifted ode field
* pue_pus_snvs: in SNVS domain, shifted ode field
*/
#define MCUX_RT_PUS_PUE 0
#define MCUX_RT_PDRV_PULL 1
#define MCUX_RT_LPSR 2
#define MCUX_RT_SNVS 3
/*
* Macro for MCUX_RT_PULL_NOPULL, which needs to set field to 0x3 if two
* properties are false
*/
#define MCUX_RT_NOPULL(node_id) \
((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
(0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \
#define Z_PINCTRL_MCUX_RT_PDRV(node_id) \
IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
(MCUX_RT_PULL_PULLDOWN << MCUX_RT_PULL_SHIFT) |) \
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
(MCUX_RT_PULL_PULLUP << MCUX_RT_PULL_SHIFT) |) \
(MCUX_RT_NOPULL(node_id) << MCUX_RT_PULL_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_PDRV_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
#define Z_PINCTRL_MCUX_RT_PUE_PUS(node_id) \
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
<< MCUX_RT_PUE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
#define Z_PINCTRL_MCUX_RT_LPSR(node_id) \
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
<< MCUX_RT_PUE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_LPSR_ODE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
#define Z_PINCTRL_MCUX_RT_SNVS(node_id) \
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
<< MCUX_RT_PUE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_SNVS_ODE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
uint32_t gpr_register; /* IOMUXC GPR register */
uint8_t gpr_shift: 5; /* bitshift for GPR register write */
uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
uint8_t gpr_val: 1; /* value to write to GPR register */
uint8_t pue_mux: 1; /* Is pinmux reg pue type */
uint8_t pdrv_mux: 1; /* Is pinmux reg pdrv type */
uint8_t lpsr_mux: 1; /* Is pinmux reg LPSR type */
uint8_t snvs_mux: 1; /* Is pinmux reg SNVS type */
};
struct pinctrl_soc_pin {
struct pinctrl_soc_pinmux pinmux;
uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
};
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define MCUX_RT_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 0), \
(.gpr_register = DT_PROP_BY_IDX(node_id, gpr, 0),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 1), \
(.gpr_shift = DT_PROP_BY_IDX(node_id, gpr, 1),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 2), \
(.gpr_val = DT_PROP_BY_IDX(node_id, gpr, 2),)) \
.pue_mux = DT_PROP(node_id, pin_pue), \
.pdrv_mux = DT_PROP(node_id, pin_pdrv), \
.lpsr_mux = DT_PROP(node_id, pin_lpsr), \
.snvs_mux = DT_PROP(node_id, pin_snvs), \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PUE_PUS(group_id),)) \
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PDRV(group_id),)) \
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_LPSR(group_id),)) \
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_SNVS(group_id),)) \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_ */

95
soc/arm/nxp_imx/rt/pinctrl_soc.h
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@ -6,97 +6,10 @@
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
#include <devicetree.h>
#include <zephyr/types.h>
#include "fsl_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
#define MCUX_RT_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
#define MCUX_RT_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
#define MCUX_RT_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
#define MCUX_RT_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT
#define MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
#define MCUX_RT_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT
#define MCUX_RT_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#define MCUX_RT_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT
#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) | \
IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
<< MCUX_RT_BIAS_PULL_UP_SHIFT) |) \
IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
<< MCUX_RT_BIAS_PULL_DOWN_SHIFT) |) \
((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
<< MCUX_RT_BIAS_BUS_HOLD_SHIFT) | \
((!DT_PROP(node_id, bias_disable)) << MCUX_RT_PULL_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_ENUM_IDX(node_id, nxp_speed) << MCUX_RT_SPEED_SHIFT) | \
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_RT_DRIVE_STRENGTH_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_RT_SLEW_RATE_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT))
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
uint32_t gpr_register; /* IOMUXC GPR register */
uint8_t gpr_shift: 5; /* bitshift for GPR register write */
uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
uint8_t pinmux_type: 4; /* Type of pinmux register */
uint8_t gpr_val: 1; /* value to write to GPR register */
};
struct pinctrl_soc_pin {
struct pinctrl_soc_pinmux pinmux;
uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
};
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define MCUX_RT_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
.pinmux_type = DT_ENUM_IDX_OR(node_id, pin_type, 0), \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 0), \
(.gpr_register = DT_PROP_BY_IDX(node_id, gpr, 0),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 1), \
(.gpr_shift = DT_PROP_BY_IDX(node_id, gpr, 1),)) \
IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 2), \
(.gpr_val = DT_PROP_BY_IDX(node_id, gpr, 2),)) \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(group_id), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
#ifdef __cplusplus
}
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
#include "pinctrl_rt10xx.h"
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#include "pinctrl_rt11xx.h"
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */