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drivers: uart: ns16550: Move all PCIe-using nodes to a PCIe bus in DTS

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The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This commit is contained in:
Johan Hedberg 2020-12-19 17:37:24 +02:00 committed by Anas Nashif
parent 7a2bddd75a
commit 1d5d5fcf49
5 changed files with 36 additions and 42 deletions
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12
drivers/serial/uart_ns16550.c
View file

@ -57,12 +57,8 @@
#define UART_NS16550_DLF_ENABLED
#endif
#if DT_INST_PROP(0, pcie) || \
DT_INST_PROP(1, pcie) || \
DT_INST_PROP(2, pcie) || \
DT_INST_PROP(3, pcie)
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
#define UART_NS16550_PCIE_ENABLED
#include <drivers/pcie/pcie.h>
#endif
@ -268,7 +264,7 @@ struct uart_ns16550_device_config {
#ifdef UART_NS16550_PCP_ENABLED
uint32_t pcp;
#endif
#ifdef UART_NS16550_PCIE_ENABLED
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
bool pcie;
pcie_bdf_t pcie_bdf;
pcie_id_t pcie_id;
@ -350,7 +346,7 @@ static int uart_ns16550_configure(const struct device *dev,
ARG_UNUSED(dev_cfg);
#ifndef UART_NS16550_ACCESS_IOPORT
#ifdef UART_NS16550_PCIE_ENABLED
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
if (dev_cfg->pcie) {
struct pcie_mbar mbar;
@ -365,7 +361,7 @@ static int uart_ns16550_configure(const struct device *dev,
device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
K_MEM_CACHE_NONE);
} else
#endif /* UART_NS16550_PCIE_ENABLED */
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
{
/* Map directly from DTS */
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);

6
drivers/serial/uart_ns16550_port_x.h
View file

@ -16,7 +16,7 @@ static void irq_config_func_@NUM@(const struct device *port);
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_@NUM@ = {
#ifdef UART_NS16550_ACCESS_IOPORT
.port = DT_INST_REG_ADDR(@NUM@),
#elif !DT_INST_PROP(@NUM@, pcie)
#elif !DT_INST_ON_BUS(@NUM@, pcie)
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(@NUM@)),
#endif
.sys_clk_freq = DT_INST_PROP(@NUM@, clock_frequency),
@ -29,7 +29,7 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_@NUM@ = {
.pcp = DT_INST_PROP(@NUM@, pcp),
#endif
#if DT_INST_PROP(@NUM@, pcie)
#if DT_INST_ON_BUS(@NUM@, pcie)
.pcie = true,
.pcie_bdf = DT_INST_REG_ADDR(@NUM@),
.pcie_id = DT_INST_REG_SIZE(@NUM@),
@ -71,7 +71,7 @@ static void irq_config_func_@NUM@(const struct device *dev)
{
ARG_UNUSED(dev);
#if DT_INST_PROP(@NUM@, pcie)
#if DT_INST_ON_BUS(@NUM@, pcie)
#if DT_INST_IRQN(@NUM@) == PCIE_IRQ_DETECT
/* PCI(e) with auto IRQ detection */

5
dts/bindings/serial/ns16550.yaml
View file

@ -22,8 +22,3 @@ properties:
type: int
required: false
description: divisor latch fraction (DLF, if supported)
pcie:
type: boolean
required: false
description: attached via PCI(e) bus

34
dts/x86/apollo_lake.dtsi
View file

@ -34,25 +34,16 @@
#interrupt-cells = <3>;
};
soc {
pcie0 {
label = "PCIE_0";
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
compatible = "intel,pcie";
ranges;
vtd: vtd@fed65000 {
compatible = "intel,vt-d";
label = "VTD_0";
reg = <0xfed65000 0x1000>;
status = "disabled";
};
uart0: uart@c000 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x18,0) PCIE_ID(0x8086,0x5abc)>;
label = "UART_0";
@ -66,7 +57,6 @@
uart1: uart@c100 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x18,1) PCIE_ID(0x8086,0x5abe)>;
label = "UART_1";
@ -81,7 +71,6 @@
uart2: uart@c200 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x18,2) PCIE_ID(0x8086,0x5ac0)>;
label = "UART_2";
@ -96,7 +85,6 @@
uart3: uart@c300 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x18,3) PCIE_ID(0x8086,0x5aee)>;
label = "UART_3";
@ -107,6 +95,22 @@
status = "okay";
current-speed = <115200>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
vtd: vtd@fed65000 {
compatible = "intel,vt-d";
label = "VTD_0";
reg = <0xfed65000 0x1000>;
status = "disabled";
};
i2c0: i2c@b000 {
compatible = "snps,designware-i2c";

21
dts/x86/elkhart_lake.dtsi
View file

@ -34,16 +34,16 @@
#interrupt-cells = <3>;
};
soc {
pcie0 {
label = "PCIE_0";
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
compatible = "intel,pcie";
ranges;
uart0: uart@f000 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x1e,0) PCIE_ID(0x8086,0x4b28)>;
label = "UART_0";
@ -57,7 +57,6 @@
uart1: uart@f100 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x1e,1) PCIE_ID(0x8086,0x4b29)>;
label = "UART_1";
@ -72,7 +71,6 @@
uart2: uart@ca00 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x19,2) PCIE_ID(0x8086,0x4b4d)>;
label = "UART_2";
@ -87,7 +85,6 @@
uart_pse_0: uart@8800 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,0) PCIE_ID(0x8086,0x4b96)>;
label = "UART_PSE_0";
@ -102,7 +99,6 @@
uart_pse_1: uart@8900 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,1) PCIE_ID(0x8086,0x4b97)>;
label = "UART_PSE_1";
@ -117,7 +113,6 @@
uart_pse_2: uart@8a00 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,2) PCIE_ID(0x8086,0x4b98)>;
label = "UART_PSE_2";
@ -132,7 +127,6 @@
uart_pse_3: uart@8b00 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,3) PCIE_ID(0x8086,0x4b99)>;
label = "UART_PSE_3";
@ -147,7 +141,6 @@
uart_pse_4: uart@8c00 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,4) PCIE_ID(0x8086,0x4b9a)>;
label = "UART_PSE_4";
@ -162,7 +155,6 @@
uart_pse_5: uart@8d00 {
compatible = "ns16550";
pcie;
reg = <PCIE_BDF(0,0x11,5) PCIE_ID(0x8086,0x4b9b)>;
label = "UART_PSE_5";
@ -173,6 +165,13 @@
status = "okay";
current-speed = <115200>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
i2c0: i2c@a800 {
compatible = "snps,designware-i2c";