drivers/crypto/crypto_it8xxx2_sha_v2.c: implement sha v2 for it82xx2 series
Implement a new version crypto_it8xxx2_sha_v2 driver for it82xx2 series. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
Ruibin Chang
Carles Cufí
parent
a3f0ae9b0f
commit
1d74cb74d9
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@ -11,5 +11,6 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_INTEL_SHA crypto_intel_sha.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_NPCX_SHA crypto_npcx_sha.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCHP_XEC_SYMCR crypto_mchp_xec_symcr.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA crypto_it8xxx2_sha.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA_V2 crypto_it8xxx2_sha_v2.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP crypto_mcux_dcp.c)
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zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
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@ -11,3 +11,14 @@ config CRYPTO_IT8XXX2_SHA
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This driver supports SHA256 hardware accelerator of the it8xxx2 series.
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It requires 256 + 256 bytes in the RAM's first 4k-bytes to calculate
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SHA256 hash.
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config CRYPTO_IT8XXX2_SHA_V2
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bool "ITE IT8XXX2 SHA V2 driver"
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default y
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depends on DT_HAS_ITE_IT8XXX2_SHA_V2_ENABLED
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select SOC_IT8XXX2_SHA256_HW_ACCELERATE
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help
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Enable ITE IT8XXX2 SHA V2 driver.
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This driver supports SHA256 hardware accelerator of the it82xx2 series.
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It requires 1024 + 256 bytes in the RAM's first 4k-bytes to calculate
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SHA256 hash.
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350
drivers/crypto/crypto_it8xxx2_sha_v2.c
Normal file
350
drivers/crypto/crypto_it8xxx2_sha_v2.c
Normal file
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@ -0,0 +1,350 @@
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/*
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* Copyright (c) 2024 ITE Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_sha_v2
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#include <zephyr/kernel.h>
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#include <zephyr/crypto/crypto.h>
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#include <zephyr/sys/byteorder.h>
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#include <chip_chipregs.h>
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#include <errno.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(sha_it8xxx2, CONFIG_CRYPTO_LOG_LEVEL);
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"support only one sha compatible node");
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#define IT8XXX2_SHA_REGS_BASE DT_REG_ADDR(DT_NODELABEL(sha0))
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/* 0x00: SHA Control Register */
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#define IT8XXX2_REG_SHACR (0x00)
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#define IT8XXX2_SEL1SHA1 BIT(6)
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#define IT8XXX2_SELSHA2ALL (BIT(5) | BIT(4))
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#define IT8XXX2_SHAWB BIT(2)
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#define IT8XXX2_SHAINI BIT(1)
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#define IT8XXX2_SHAEXE BIT(0)
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/* 0x01: SHA Status Register */
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#define IT8XXX2_REG_SHASR (0x01)
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#define IT8XXX2_SHAIE BIT(3)
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#define IT8XXX2_SHAIS BIT(2)
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#define IT8XXX2_SHABUSY BIT(0)
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/* 0x02: SHA Execution Counter Register */
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#define IT8XXX2_REG_SHAECR (0x02)
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#define IT8XXX2_SHAEXEC_64Byte 0x0
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#define IT8XXX2_SHAEXEC_512Byte 0x7
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#define IT8XXX2_SHAEXEC_1KByte 0xf
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/* 0x03: SHA DLM Base Address 0 Register */
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#define IT8XXX2_REG_SHADBA0R (0x03)
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/* 0x04: SHA DLM Base Address 1 Register */
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#define IT8XXX2_REG_SHADBA1R (0x04)
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#define SHA_SHA256_HASH_LEN 32
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#define SHA_SHA256_BLOCK_LEN 64
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#define SHA_SHA256_SRAM_BUF 1024
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#define SHA_SHA256_HASH_LEN_WORDS (SHA_SHA256_HASH_LEN / sizeof(uint32_t))
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#define SHA_SHA256_BLOCK_LEN_WORDS (SHA_SHA256_BLOCK_LEN / sizeof(uint32_t))
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#define SHA_SHA256_SRAM_BUF_WORDS (SHA_SHA256_SRAM_BUF / sizeof(uint32_t))
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#define SHA_SHA256_CALCULATE_TIMEOUT_US 150
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#define SHA_SHA256_WRITE_BACK_TIMEOUT_US 45
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#define SHA_SHA256_WAIT_NEXT_CLOCK_TIME_US 15
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/*
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* This struct is used by the hardware and must be stored in RAM first 4k-byte
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* and aligned on a 256-byte boundary.
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*/
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struct chip_sha256_ctx {
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union {
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/* SHA data buffer */
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uint32_t w_sha[SHA_SHA256_SRAM_BUF_WORDS];
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uint8_t w_input[SHA_SHA256_SRAM_BUF];
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};
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/* H[0] ~ H[7] */
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uint32_t h[SHA_SHA256_HASH_LEN_WORDS];
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uint32_t sha_init;
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uint32_t w_input_index;
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uint32_t total_len;
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} __aligned(256);
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Z_GENERIC_SECTION(.__sha256_ram_block) struct chip_sha256_ctx chip_ctx;
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static void it8xxx2_sha256_init(bool init_k)
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{
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chip_ctx.sha_init = init_k;
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chip_ctx.w_input_index = 0;
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chip_ctx.total_len = 0;
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/* Set DLM address for input data */
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sys_write8(((uint32_t)&chip_ctx) & 0xc0,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHADBA0R);
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sys_write8(((uint32_t)&chip_ctx) >> 8,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHADBA1R);
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}
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static int it8xxx2_sha256_module_calculation(void)
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{
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struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
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uint32_t key, count;
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uint8_t sha_ctrl;
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bool timeout = true;
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sha_ctrl = sys_read8(IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHACR);
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if (chip_ctx.sha_init) {
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sha_ctrl |= (IT8XXX2_SHAINI | IT8XXX2_SHAEXE);
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chip_ctx.sha_init = 0;
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} else {
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sha_ctrl |= IT8XXX2_SHAEXE;
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}
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/*
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* Global interrupt is disabled because the CPU cannot access memory
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* via the DLM (Data Local Memory) bus while HW module is computing
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* hash.
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*/
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key = irq_lock();
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/* Crypto use SRAM */
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gctrl_regs->GCTRL_PMER3 |= IT8XXX2_GCTRL_SRAM_CRYPTO_USED;
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sys_write8(sha_ctrl, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHACR);
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/*
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* HW 64 bytes data calculation ~= 4us;
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* HW 1024 bytes data calculation ~= 66us.
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*/
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for (count = 0; count <= (SHA_SHA256_CALCULATE_TIMEOUT_US /
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SHA_SHA256_WAIT_NEXT_CLOCK_TIME_US); count++) {
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/* Delay 15us */
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gctrl_regs->GCTRL_WNCKR = IT8XXX2_GCTRL_WN65K;
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if ((sys_read8(IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHASR) & IT8XXX2_SHAIS)) {
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timeout = 0;
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break;
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}
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}
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sys_write8(IT8XXX2_SHAIS, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHASR);
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/* CPU use SRAM */
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gctrl_regs->GCTRL_PMER3 &= ~IT8XXX2_GCTRL_SRAM_CRYPTO_USED;
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gctrl_regs->GCTRL_PMER3;
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irq_unlock(key);
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if (timeout) {
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LOG_ERR("HW execute sha256 calculation timeout");
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it8xxx2_sha256_init(true);
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return -ETIMEDOUT;
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}
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chip_ctx.w_input_index = 0;
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return 0;
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}
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static int it8xxx2_hash_handler(struct hash_ctx *ctx, struct hash_pkt *pkt,
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bool finish)
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{
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struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
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uint32_t rem_len = pkt->in_len;
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uint32_t in_buf_idx = 0;
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uint32_t i, key, count;
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uint8_t sha_ctrl;
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bool timeout = true;
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int ret;
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while (rem_len) {
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/* Data length >= 1KB */
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if (rem_len >= SHA_SHA256_SRAM_BUF) {
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rem_len = rem_len - SHA_SHA256_SRAM_BUF;
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for (i = 0; i < SHA_SHA256_SRAM_BUF; i++) {
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chip_ctx.w_input[chip_ctx.w_input_index++] =
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pkt->in_buf[in_buf_idx++];
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}
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/* HW automatically load 1KB data from DLM */
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sys_write8(IT8XXX2_SHAEXEC_1KByte,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHAECR);
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ret = it8xxx2_sha256_module_calculation();
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if (ret) {
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return ret;
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}
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} else {
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/* 0 <= Data length < 1KB */
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while (rem_len) {
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rem_len--;
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chip_ctx.w_input[chip_ctx.w_input_index++] =
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pkt->in_buf[in_buf_idx++];
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/*
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* If fill full 64byte then execute HW calculation.
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* If not, will execute in later finish block.
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*/
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if (chip_ctx.w_input_index >= SHA_SHA256_BLOCK_LEN) {
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/* HW automatically load 64Bytes data from DLM */
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sys_write8(IT8XXX2_SHAEXEC_64Byte,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHAECR);
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ret = it8xxx2_sha256_module_calculation();
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if (ret) {
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return ret;
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}
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}
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}
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}
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}
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chip_ctx.total_len += pkt->in_len;
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if (finish) {
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uint32_t *ob_ptr = (uint32_t *)pkt->out_buf;
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/* Pre-processing (Padding) */
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memset(&chip_ctx.w_input[chip_ctx.w_input_index],
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0, SHA_SHA256_BLOCK_LEN - chip_ctx.w_input_index);
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chip_ctx.w_input[chip_ctx.w_input_index] = 0x80;
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/*
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* Handles the boundary case of rest data:
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* Because the last eight bytes are bit length field of sha256 rule.
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* If the data index >= 56, it needs to trigger HW to calculate,
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* then fill 0 data and the last eight bytes bit length, and calculate again.
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*/
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if (chip_ctx.w_input_index >= 56) {
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/* HW automatically load 64Bytes data from DLM */
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sys_write8(IT8XXX2_SHAEXEC_64Byte,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHAECR);
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ret = it8xxx2_sha256_module_calculation();
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if (ret) {
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return ret;
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}
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memset(&chip_ctx.w_input[chip_ctx.w_input_index],
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0, SHA_SHA256_BLOCK_LEN - chip_ctx.w_input_index);
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}
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/*
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* Since input data (big-endian) are copied 1byte by 1byte to
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* it8xxx2 memory (little-endian), so the bit length needs to
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* be transformed into big-endian format and then write to memory.
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*/
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chip_ctx.w_sha[15] = sys_cpu_to_be32(chip_ctx.total_len * 8);
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/* HW automatically load 64Bytes data from DLM */
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sys_write8(IT8XXX2_SHAEXEC_64Byte, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHAECR);
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ret = it8xxx2_sha256_module_calculation();
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if (ret) {
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return ret;
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}
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/* HW write back the hash result to DLM */
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/* Set DLM address for input data */
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sys_write8(((uint32_t)&chip_ctx.h) & 0xc0,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHADBA0R);
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sys_write8(((uint32_t)&chip_ctx.h) >> 8,
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IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHADBA1R);
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key = irq_lock();
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/* Crypto use SRAM */
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gctrl_regs->GCTRL_PMER3 |= IT8XXX2_GCTRL_SRAM_CRYPTO_USED;
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sha_ctrl = sys_read8(IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHACR);
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sys_write8(sha_ctrl | IT8XXX2_SHAWB, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHACR);
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/* HW write back the hash result to DLM ~= 1us */
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for (count = 0; count <= (SHA_SHA256_WRITE_BACK_TIMEOUT_US /
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SHA_SHA256_WAIT_NEXT_CLOCK_TIME_US); count++) {
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/* Delay 15us */
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gctrl_regs->GCTRL_WNCKR = IT8XXX2_GCTRL_WN65K;
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if ((sys_read8(IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHASR)
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& IT8XXX2_SHAIS)) {
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timeout = 0;
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break;
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}
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}
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sys_write8(IT8XXX2_SHAIS, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHASR);
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/* CPU use SRAM */
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gctrl_regs->GCTRL_PMER3 &= ~IT8XXX2_GCTRL_SRAM_CRYPTO_USED;
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gctrl_regs->GCTRL_PMER3;
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irq_unlock(key);
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if (timeout) {
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LOG_ERR("HW write back hash timeout");
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it8xxx2_sha256_init(true);
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return -ETIMEDOUT;
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}
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for (i = 0; i < SHA_SHA256_HASH_LEN_WORDS; i++) {
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ob_ptr[i] = chip_ctx.h[i];
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}
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it8xxx2_sha256_init(true);
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}
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return 0;
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}
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static int it8xxx2_hash_session_free(const struct device *dev,
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struct hash_ctx *ctx)
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{
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it8xxx2_sha256_init(true);
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return 0;
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}
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static inline int it8xxx2_query_hw_caps(const struct device *dev)
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{
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return (CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS);
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}
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static int it8xxx2_hash_begin_session(const struct device *dev,
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struct hash_ctx *ctx, enum hash_algo algo)
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{
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if (algo != CRYPTO_HASH_ALGO_SHA256) {
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LOG_ERR("Unsupported algorithm");
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return -EINVAL;
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}
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if (ctx->flags & ~(it8xxx2_query_hw_caps(dev))) {
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LOG_ERR("Unsupported flag");
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return -EINVAL;
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}
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it8xxx2_sha256_init(true);
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ctx->hash_hndlr = it8xxx2_hash_handler;
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return 0;
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}
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static int it8xxx2_sha_init(const struct device *dev)
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{
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struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
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/* CPU use SRAM */
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gctrl_regs->GCTRL_PMER3 &= ~IT8XXX2_GCTRL_SRAM_CRYPTO_USED;
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gctrl_regs->GCTRL_PMER3;
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it8xxx2_sha256_init(true);
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/* Select SHA-2 Family, SHA-256 */
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sys_write8(0, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHACR);
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/* SHA interrupt disable */
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sys_write8(0, IT8XXX2_SHA_REGS_BASE + IT8XXX2_REG_SHASR);
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return 0;
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}
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static struct crypto_driver_api it8xxx2_crypto_api = {
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.hash_begin_session = it8xxx2_hash_begin_session,
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.hash_free_session = it8xxx2_hash_session_free,
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.query_hw_caps = it8xxx2_query_hw_caps,
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};
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DEVICE_DT_INST_DEFINE(0, &it8xxx2_sha_init, NULL, NULL, NULL, POST_KERNEL,
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CONFIG_CRYPTO_INIT_PRIORITY, &it8xxx2_crypto_api);
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12
dts/bindings/crypto/ite,it8xxx2-sha-v2.yaml
Normal file
12
dts/bindings/crypto/ite,it8xxx2-sha-v2.yaml
Normal file
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# Copyright (c) 2024, ITE Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: ITE IT8XXX2 Crypto SHA accelerator V2.
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compatible: "ite,it8xxx2-sha-v2"
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include: base.yaml
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properties:
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reg:
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required: true
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@ -998,5 +998,11 @@
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num-in-endpoints = <10>;
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num-out-endpoints = <5>;
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};
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sha0: crypto@f03c00 {
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compatible = "ite,it8xxx2-sha-v2";
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reg = <0x00f03c00 0x5>;
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status = "disabled";
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};
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};
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};
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@ -1633,6 +1633,8 @@ struct gctrl_it8xxx2_regs {
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/* 0x06: Reset Status */
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#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0))
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#define IT8XXX2_GCTRL_IWDTR BIT(1)
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/* 0x0B: Wait Next 65K Rising */
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#define IT8XXX2_GCTRL_WN65K 0x00
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/* 0x10: Reset Control DMM */
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#define IT8XXX2_GCTRL_UART1SD BIT(3)
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#define IT8XXX2_GCTRL_UART2SD BIT(2)
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@ -1652,6 +1654,7 @@ struct gctrl_it8xxx2_regs {
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#define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0)
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/* 0x46: Pin Multi-function Enable 3 */
|
||||
#define IT8XXX2_GCTRL_SMB3PSEL BIT(6)
|
||||
#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED BIT(5)
|
||||
/* 0x4B: ETWD and UART Control */
|
||||
#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0)
|
||||
/* 0x5D: RISCV ILM Configuration 0 */
|
||||
|
|
|
|||
|
|
@ -168,6 +168,11 @@ config SOC_IT8XXX2_SHA256_HW_ACCELERATE
|
|||
If we enable this config, because HW limits, the sha256 data must place in
|
||||
first 4KB of RAM.
|
||||
|
||||
config SOC_IT8XXX2_SHA256_BLOCK_SIZE
|
||||
hex
|
||||
default 0x500 if SOC_IT82002_AW || SOC_IT82202_AX || SOC_IT82302_AX
|
||||
default 0x200
|
||||
|
||||
DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash
|
||||
|
||||
config SOC_IT8XXX2_FLASH_SIZE_BYTES
|
||||
|
|
|
|||
|
|
@ -65,10 +65,6 @@
|
|||
#define MPU_ALIGN(region_size) . = ALIGN(4)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
|
||||
#define SHA256_BLOCK_SIZE 0x200
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/linker-devnull.h>
|
||||
|
||||
MEMORY
|
||||
|
|
@ -161,7 +157,7 @@ SECTIONS
|
|||
/* Pad to match allocation of block in RAM,
|
||||
* maintaining code alignment against ILM */
|
||||
__sha256_pad_block_start = .;
|
||||
. = . + SHA256_BLOCK_SIZE;
|
||||
. = . + CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE;
|
||||
#endif
|
||||
/* Specially-tagged functions in SoC sources */
|
||||
KEEP(*(.__ram_code))
|
||||
|
|
@ -249,10 +245,11 @@ SECTIONS
|
|||
__sha256_ram_block_size = \
|
||||
ABSOLUTE(. - __sha256_ram_block_start);
|
||||
__sha256_ram_block_end = .;
|
||||
ASSERT((__sha256_ram_block_size == SHA256_BLOCK_SIZE), \
|
||||
"We need 512bytes for HW sha256 module");
|
||||
|
||||
ASSERT((__sha256_ram_block_size == CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE), \
|
||||
"Not compatible ram size for HW sha256 module");
|
||||
ASSERT((__sha256_ram_block_end < (RAM_BASE + 0x1000)), \
|
||||
"512bytes must in SRAM first 4kbytes");
|
||||
"sha256 ram block must in SRAM first 4kbytes");
|
||||
ASSERT(((ABSOLUTE(__sha256_ram_block_start) & 0xfff) == \
|
||||
(ABSOLUTE(__sha256_pad_block_start) & 0xfff)), \
|
||||
"sha256 ram block needs the same offset with sha256 rom block");
|
||||
|
|
|
|||
Loading…
Reference in a new issue