soc/intel_s1000: Add new cAVS shim & IDC interfaces
This board, whose hardware is just a cAVS 1.8 device without an x86 host CPU, started life (as all the cAVS devices did) as a cut-and-pasted copy of the same basic code. Because of hardware and schedule limitations, it didn't get the same unification treatment that all the other platforms did. But it turns out that in SMP configurations (which... it's not clear if we actually test on hardware?) it wants to use the cavs_timer driver, which now uses the new SOC API and not the old one. Which s1000 doesn't expose. So... I guess we have to continue to cut and paste until we can find time to unify this. Add a copy of the new shim/IDC headers to this SOC and expose them via devivcetree. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
33c97f6116
commit
1e1830de95
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@ -49,6 +49,11 @@
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#interrupt-cells = <3>;
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};
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shim: shim@71f00 {
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compatible = "intel,cavs-shim";
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reg = <0x71f00 0x100>;
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};
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cavs0: cavs@78800 {
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compatible = "intel,cavs-intc";
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reg = <0x78800 0x10>;
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148
soc/xtensa/intel_s1000/include/cavs-idc.h
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148
soc/xtensa/intel_s1000/include/cavs-idc.h
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/*
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_
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#define ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_
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/*
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* (I)ntra (D)SP (C)ommunication is the facility for sending
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* interrupts directly between DSP cores. The interface
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* is... somewhat needlessly complicated.
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*
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* Each core has a set of registers its is supposed to use, but all
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* registers seem to behave symmetrically regardless of which CPU does
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* the access.
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*
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* Each core has a "ITC" register associated with each other core in
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* the system (including itself). When the high bit becomes 1 in an
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* ITC register, an IDC interrupt is latched for the target core.
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* Data in other bits is stored but otherwise ignored, it's merely
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* data to be transmitted along with the interrupt.
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*
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* On the target core, there is a "TFC" register for each core that
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* reflects the same value written to ITC. In fact experimentally
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* these seem to be the same register at different addresses. When
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* the high bit of TFC is written with a 1, the value becomes ZERO,
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* indicating an acknowledgment of the interrupt. This action can
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* also latch an interrupt to send back to the originator if unmasked
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* (see below).
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*
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* (There is also an IETC/TEFC register pair that stores 30 bits of
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* data but otherwise has no hardware behavior. This is probably best
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* ignored for new protocols, as experimentally it seems to provide no
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* performance benefit vs. storing a message in RAM. The cAVS 1.5/1.8
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* ROM boot protocol uses it to store an entry point address, though.)
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*
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* So you can send a synchronous message from core "src" (where src is
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* the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
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* core "dst" with:
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*
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* IDC[src].core[dst].itc = BIT(31) | message;
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* while (IDC[src].core[dst].itc & BIT(31)) {}
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*
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* And the other side (on cpu "dst", generally in the IDC interruupt
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* handler) will read and acknowledge those same values via:
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*
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* uint32_t my_msg = IDC[dst].core[src].tfc & 0x7fffffff;
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* IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
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*
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* And for clarity, at all times and for all cores and all pairs of src/dst:
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*
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* IDC[src].core[dst].itc == IDC[dst].core[src].tfc
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*
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* Finally note the two control registers at the end of each core's
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* register block, which store a bitmask of cores that are allowed to
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* send that core an interrupt via either ITC (set high "BUSY" bit) or
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* TFC (clear high "DONE" bit). This masking is in ADDITION to the
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* level 2 bit for IDC in the per-core INTCTRL DSP register AND the
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* Xtensa architectural INTENABLE SR. You must enable IDC interrupts
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* form core "src" to core "dst" with:
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*
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* IDC[dst].busy_int |= BIT(src) // Or disable with "&= ~BIT(src)" of course
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*/
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struct cavs_idc {
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struct {
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uint32_t tfc; /* (T)arget (F)rom (C)ore */
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uint32_t tefc; /* ^^ + (E)xtension */
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uint32_t itc; /* (I)nitiator (T)o (C)ore */
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uint32_t ietc; /* ^^ + (E)xtension */
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} core[4];
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uint32_t unused0[4];
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uint8_t busy_int; /* bitmask of cores that can IDC via ITC */
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uint8_t done_int; /* bitmask of cores that can IDC via TFC */
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uint8_t unused1;
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uint8_t unused2;
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uint32_t unused3[11];
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};
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#define IDC ((volatile struct cavs_idc *)DT_REG_ADDR(DT_NODELABEL(idc)))
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extern void soc_idc_init(void);
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/* cAVS interrupt mask bits. Each core has one of these structs
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* indexed in the intctrl[] array. Each external interrupt source
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* indexes one bit in one of the state substructs (one each for Xtensa
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* level 2-5 interrupts). The "mask" field shows the current masking
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* state, with a 1 representing "interrupt disabled". The "status"
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* field indicates interrupts that are currently latched and awaiting
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* delivery. Write bits to "set" to set the mask bit to 1 and disable
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* interrupts. Write a 1 bit to "clear" to force the mask bit to 0
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* and enable them. For example, for core "c":
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*
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* INTCTRL[c].l2.clear = 0x10; // unmask IDC interrupt
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*
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* INTCTRL[c].l3.set = 0xffffffff; // Mask all L3 interrupts
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*
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* Note that this interrupt controller is separate from the Xtensa
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* architectural interrupt hardware controlled by the
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* INTENABLE/INTERRUPT/INTSET/INTCLEAR special registers on each core
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* which much also be configured for interrupts to arrive. Note also
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* that some hardware (like IDC, see above) implements a third (!)
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* layer of interrupt masking.
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*/
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struct cavs_intctrl {
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struct {
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uint32_t set, clear, mask, status;
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} l2, l3, l4, l5;
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};
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/* Named interrupt bits in the above registers */
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#define CAVS_L2_HPGPDMA BIT(24) /* HP General Purpose DMA */
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#define CAVS_L2_DWCT1 BIT(23) /* DSP Wall Clock Timer 1 */
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#define CAVS_L2_DWCT0 BIT(22) /* DSP Wall Clock Timer 0 */
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#define CAVS_L2_L2ME BIT(21) /* L2 Memory Error */
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#define CAVS_L2_DTS BIT(20) /* DSP Timestamping */
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#define CAVS_L2_SHA BIT(16) /* SHA-256 */
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#define CAVS_L2_DCLC BIT(15) /* Demand Cache Line Command */
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#define CAVS_L2_IDC BIT(8) /* IDC */
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#define CAVS_L2_HIPC BIT(7) /* Host IPC */
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#define CAVS_L2_MIPC BIT(6) /* CSME IPC */
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#define CAVS_L2_PIPC BIT(5) /* PMC IPC */
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#define CAVS_L2_SIPC BIT(4) /* Sensor Hub IPC */
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#define CAVS_L3_DSPGCL BIT(31) /* DSP Gateway Code Loader */
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#define CAVS_L3_DSPGHOS(n) BIT(16 + n) /* DSP Gateway Host Output Stream */
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#define CAVS_L3_HPGPDMA BIT(15) /* HP General Purpose DMA */
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#define CAVS_L3_DSPGHIS(n) BIT(n) /* DSP Gateway Host Input Stream */
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#define CAVS_L4_DSPGLOS(n) BIT(16 + n) /* DSP Gateway Link Output Stream */
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#define CAVS_L4_LPGPGMA BIT(15) /* LP General Purpose DMA */
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#define CAVS_L4_DSPGLIS(n) BIT(n) /* DSP Gateway Link Input Stream */
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#define CAVS_L5_LPGPDMA BIT(16) /* LP General Purpose DMA */
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#define CAVS_L5_DWCT1 BIT(15) /* DSP Wall CLock Timer 1 */
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#define CAVS_L5_DWCT0 BIT(14) /* DSP Wall Clock Timer 0 */
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#define CAVS_L5_DMIX BIT(13) /* Digital Mixer */
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#define CAVS_L5_ANC BIT(12) /* Active Noise Cancellation */
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#define CAVS_L5_SNDW BIT(11) /* SoundWire */
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#define CAVS_L5_SLIM BIT(10) /* Slimbus */
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#define CAVS_L5_DSPK BIT(9) /* Digital Speaker */
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#define CAVS_L5_DMIC BIT(8) /* Digital Mic */
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#define CAVS_L5_I2S(n) BIT(n) /* I2S */
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#define CAVS_INTCTRL \
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((volatile struct cavs_intctrl *)DT_REG_ADDR(DT_NODELABEL(cavs0)))
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#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_ */
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144
soc/xtensa/intel_s1000/include/cavs-shim.h
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144
soc/xtensa/intel_s1000/include/cavs-shim.h
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/*
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
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#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
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/* The "shim" block contains most of the general system control
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* registers on cAVS platforms. While the base address changes, it
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* has remained largely, but not perfectly, compatible between
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* versions.
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*/
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#ifndef _ASMLANGUAGE
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struct cavs_shim {
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uint32_t skuid;
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uint32_t _unused0[7];
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uint32_t dspwc_lo;
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uint32_t dspwc_hi;
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uint32_t dspwctcs;
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uint32_t _unused1[1];
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uint32_t dspwct0c_lo;
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uint32_t dspwct0c_hi;
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uint32_t dspwct1c_lo;
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uint32_t dspwct1c_hi;
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uint32_t _unused2[14];
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uint32_t clkctl;
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uint32_t clksts;
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uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
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uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
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uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
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uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
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uint16_t pwrctl;
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uint16_t pwrsts;
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uint32_t lpsctl;
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uint32_t lpsdmas0;
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uint32_t lpsdmas1;
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uint32_t spsreq;
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uint32_t ldoctl;
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uint32_t _unused3[2];
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union {
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/* cAVS 1.5 */
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struct {
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uint32_t hspgists;
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uint32_t lspgists;
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uint32_t _unused4[2];
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};
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/* cAVS 1.8+ */
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struct {
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uint32_t lpsalhss0;
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uint32_t lpsalhss1;
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uint32_t lpsalhss2;
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uint32_t lpsalhss3;
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};
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};
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uint32_t _unused5[4];
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uint32_t l2mecs;
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uint32_t l2mpat;
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uint32_t _unused6[2];
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uint32_t ltrc;
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uint32_t _unused8[3];
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uint32_t dbgo;
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uint32_t svcfg;
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uint32_t _unused9[2];
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};
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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uint32_t l2lmcap;
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uint32_t l2lmpat;
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uint32_t _unused0[2];
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uint32_t hspgctl0;
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uint32_t hsrmctl0;
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uint32_t hspgists0;
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uint32_t _unused1;
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uint32_t hspgctl1;
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uint32_t hsrmctl1;
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uint32_t hspgists1;
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uint32_t _unused2[9];
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uint32_t lspgctl;
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uint32_t lsrmctl;
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uint32_t lspgists;
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};
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#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
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/* Host memory window control. Not strictly part of the shim block. */
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struct cavs_win {
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uint32_t dmwba;
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uint32_t dmwlo;
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};
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#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win)))
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* cAVS 1.8+ CLKCTL bits */
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#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
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#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
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#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */
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#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
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#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */
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#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
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#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
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#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
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#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
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/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */
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#define CAVS15_CLKCTL_RAPLLC BIT(31)
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#define CAVS15_CLKCTL_RFROSCC BIT(29)
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#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28)
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#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x)
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#define CAVS15_CLKCTL_SLIMFDCGB BIT(25)
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#define CAVS15_CLKCTL_DMICFDCGB BIT(24)
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#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x)
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#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x)
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#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */
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#define CAVS15_CLKCTL_TCPAPLLS BIT(7)
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#define CAVS15_CLKCTL_LDCS BIT(5)
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#define CAVS15_CLKCTL_HDCS BIT(4)
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#define CAVS15_CLKCTL_LDOCS BIT(3)
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#define CAVS15_CLKCTL_HDOCS BIT(2)
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#define CAVS15_CLKCTL_LMPCS BIT(1)
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#define CAVS15_CLKCTL_HMPCS BIT(0)
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#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
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#ifdef SOC_SERIES_INTEL_CAVS_V25
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# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
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# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16)
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#else
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# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
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# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
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#endif
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#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
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#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
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#define CAVS_DMWBA_ENABLE BIT(0)
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#define CAVS_DMWBA_READONLY BIT(1)
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#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */
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