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boards: remove obsolete CTB board

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This board is not supported and not available for general public.
Use the Quark SE CRB/Devboard instead.

Change-Id: Id0f8c08bbacb812ef00fe9502b4acecf4f31ffd7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2016-02-13 00:22:07 -05:00 committed by Gerrit Code Review
parent f5a31b9550
commit 1e57226ae6
25 changed files with 16 additions and 552 deletions
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8
boards/quark_se_ctb/Kconfig
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@ -1,8 +0,0 @@
if BOARD_QUARK_SE_CTB
config BOARD
default "quark_se_ctb"
endif # BOARD_QUARK_SE_CTB

5
boards/quark_se_ctb/Kconfig.board
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@ -1,5 +0,0 @@
config BOARD_QUARK_SE_CTB
bool "Quark SE Test Board"
select SOC_QUARK_SE
depends on X86

6
boards/quark_se_ctb/Makefile
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@ -1,6 +0,0 @@
ccflags-y += -I$(srctree)/include/drivers
ccflags-y += -I$(srctree)/drivers
asflags-y := ${ccflags-y}
obj-y += board.o
obj-$(CONFIG_PINMUX) += pinmux.o

21
boards/quark_se_ctb/board.c
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@ -1,21 +0,0 @@
/*
* Copyright (c) 2011-2015, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <nanokernel.h>
#include "board.h"
#include <uart.h>
#include <device.h>
#include <init.h>

22
boards/quark_se_ctb/board.h
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@ -1,22 +0,0 @@
/*
* Copyright (c) 2015 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
#endif /* __INC_BOARD_H */

350
boards/quark_se_ctb/pinmux.c
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@ -1,350 +0,0 @@
/* pinmux.c - general pinmux operation */
/*
* Copyright (c) 2015 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <pinmux.h>
#include <sys_io.h>
#include "pinmux/pinmux.h"
#ifndef CONFIG_PINMUX_DEV
#define PRINT(...) {; }
#else
#if defined(CONFIG_PRINTK)
#include <misc/printk.h>
#define PRINT printk
#elif defined(CONFIG_STDOUT_CONSOLE)
#define PRINT printf
#endif /* CONFIG_PRINTK */
#endif /*CONFIG_PINMUX_DEV */
#define MASK_2_BITS 0x3
#define PINMUX_PULLUP_OFFSET 0x00
#define PINMUX_SLEW_OFFSET 0x10
#define PINMUX_INPUT_OFFSET 0x20
#define PINMUX_SELECT_OFFSET 0x30
#define PINMUX_SELECT_REGISTER(base, reg_offset) \
(base + PINMUX_SELECT_OFFSET + (reg_offset << 2))
/*
* A little decyphering of what is going on here:
*
* Each pinmux register rperesents a bank of 16 pins, 2 bits per pin for a total
* of four possible settings per pin.
*
* The first argument to the macro is name of the uint32_t's that is being used
* to contain the bit patterns for all the configuration registers. The pin
* number divided by 16 selects the correct register bank based on the pin
* number.
*
* The pin number % 16 * 2 selects the position within the register bank for the
* bits controlling the pin.
*
* All but the lower two bits of the config values are masked off to ensure
* that we don't inadvertently affect other pins in the register bank.
*/
#define PIN_CONFIG(A, _pin, _func) \
(A[((_pin) / 16)] |= ((0x3 & (_func)) << (((_pin) % 16) * 2)))
/*
* This is the full pinmap that we have available on the board for configuration
* including the ball position and the various modes that can be set. In the
* _pinmux_defaults we do not spend any time setting values that are using mode
* A as the hardware brings up all devices by default in mode A.
*/
/* pin, ball, mode A, mode B, mode C */
/* 0 F02, gpio_0, ain_0, spi_s_cs */
/* 1 G04, gpio_1, ain_1, spi_s_miso */
/* 2 H05, gpio_2, ain_2, spi_s_sck */
/* 3 J06, gpio_3, ain_3, spi_s_mosi */
/* 4 K06, gpio_4, ain_4, NA */
/* 5 L06, gpio_5, ain_5, NA */
/* 6 H04, gpio_6, ain_6, NA */
/* 7 G03, gpio_7, ain_7, NA */
/* 8 L05, gpio_ss_0, ain_8, uart1_cts */
/* 9 M05, gpio_ss_1, ain_9, uart1_rts */
/* 10 K05, gpio_ss_2, ain_10 */ /* AD0 */
/* 11 G01, gpio_ss_3, ain_11 */ /* AD1 */
/* 12 J04, gpio_ss_4, ain_12 */ /* AD2 */
/* 13 G02, gpio_ss_5, ain_13 */ /* AD3 */
/* 14 F01, gpio_ss_6, ain_14 */ /* AD4 */
/* 15 J05, gpio_ss_7, ain_15 */ /* AD5 */
/* 16 L04, gpio_ss_8, ain_16, uart1_txd */ /* IO1 */
/* 17 M04, gpio_ss_9, ain_17, uart1_rxd */ /* IO0 */
/* 18 K04, uart0_rx, ain_18, NA */
/* 19 B02, uart0_tx, gpio_31, NA */
/* 20 C01, i2c0_scl, NA, NA */
/* 21 C02, i2c0_sda, NA, NA */
/* 22 D01, i2c1_scl, NA, NA */
/* 23 D02, i2c1_sda, NA, NA */
/* 24 E01, i2c0_ss_sda, NA, NA */
/* 25 E02, i2c0_ss_scl, NA, NA */
/* 26 B03, i2c1_ss_sda, NA, NA */
/* 27 A03, i2c1_ss_scl, NA, NA */
/* 28 C03, spi0_ss_miso, NA, NA */
/* 29 E03, spi0_ss_mosi, NA, NA */
/* 30 D03, spi0_ss_sck, NA, NA */
/* 31 D04, spi0_ss_cs0, NA, NA */
/* 32 C04, spi0_ss_cs1, NA, NA */
/* 33 B04, spi0_ss_cs2, gpio_29, NA */
/* 34 A04, spi0_ss_cs3, gpio_30, NA */
/* 35 B05, spi1_ss_miso, NA, NA */
/* 36 C05, spi1_ss_mosi, NA, NA */
/* 37 D05, spi1_ss_sck, NA, NA */
/* 38 E05, spi1_ss_cs0, NA, NA */
/* 39 E04, spi1_ss_cs1, NA, NA */
/* 40 A06, spi1_ss_cs2, uart0_cts, NA */
/* 41 B06, spi1_ss_cs3, uart0_rts, NA */
/* 42 C06, gpio_8, spi1_m_sck, NA */ /* IO13 */
/* 43 D06, gpio_9, spi1_m_miso, NA */ /* IO12 */
/* 44 E06, gpio_10, spi1_m_mosi, NA */ /* IO11 */
/* 45 D07, gpio_11, spi1_m_cs0, NA */ /* IO10 */
/* 46 C07, gpio_12, spi1_m_cs1, NA */
/* 47 B07, gpio_13, spi1_m_cs2, NA */
/* 48 A07, gpio_14, spi1_m_cs3, NA */
/* 49 B08, gpio_15, i2s_rxd, NA */ /* IO5 */
/* 50 A08, gpio_16, i2s_rscki, NA */ /* IO8 */
/* 51 B09, gpio_17, i2s_rws, NA */ /* IO3 */
/* 52 A09, gpio_18, i2s_tsck, NA */ /* IO2 */
/* 53 C09, gpio_19, i2s_twsi, NA */ /* IO4 */
/* 54 D09, gpio_20, i2s_txd, NA */ /* IO7 */
/* 55 D08, gpio_21, spi0_m_sck, NA */
/* 56 E07, gpio_22, spi0_m_miso, NA */
/* 57 E09, gpio_23, spi0_m_mosi, NA */
/* 58 E08, gpio_24, spi0_m_cs0, NA */
/* 59 A10, gpio_25, spi0_m_cs1, NA */
/* 60 B10, gpio_26, spi0_m_cs2, NA */
/* 61 C10, gpio_27, spi0_m_cs3, NA */
/* 62 D10, gpio_28, NA, NA */
/* 63 E10, gpio_ss_10, pwm_0, NA */ /* IO3 */
/* 64 D11, gpio_ss_11, pwm_1, NA */ /* IO5 */
/* 65 C11, gpio_ss_12, pwm_2, NA */ /* IO6 */
/* 66 B11, gpio_ss_13, pwm_3, NA */ /* IO9 */
/* 67 D12, gpio_ss_14, clkout_32khz, NA */
/* 68 C12, gpio_ss_15, clkout_16mhz, NA */
/*
* On the QUARK_SE platform there are a minimum of 69 pins that can be possibly
* set. This would be a total of 5 registers to store the configuration as per
* the bit description from above
*/
#define PINMUX_MAX_REGISTERS 5
static void _pinmux_defaults(uint32_t base)
{
uint32_t mux_config[PINMUX_MAX_REGISTERS] = { 0, 0, 0, 0, 0};
int i = 0;
PIN_CONFIG(mux_config, 0, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 1, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 2, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 3, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 4, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 5, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 7, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 8, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 9, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 16, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 17, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 40, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 41, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 42, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 43, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 44, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 45, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 63, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 64, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 65, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 66, PINMUX_FUNC_B);
for (i = 0; i < PINMUX_MAX_REGISTERS; i++) {
PRINT("PINMUX: configuring register i=%d reg=%x", i,
mux_config[i]);
sys_write32(mux_config[i], PINMUX_SELECT_REGISTER(base, i));
}
}
static inline void _pinmux_pullups(uint32_t base_address) { };
static uint32_t _quark_se_set_mux(uint32_t base, uint32_t pin, uint8_t func)
{
/*
* the registers are 32-bit wide, but each pin requires 1 bit
* to set the input enable bit.
*/
uint32_t register_offset = (pin / 32) * 4;
/*
* Now figure out what is the full address for the register
* we are looking for. Add the base register to the register_mask
*/
volatile uint32_t *mux_register = (uint32_t *)(base + register_offset);
/*
* Finally grab the pin offset within the register
*/
uint32_t pin_offset = pin % 32;
/*
* MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a
* 32-bit register.
*/
(*(mux_register)) = ((*(mux_register)) & ~(0x1 << pin_offset)) |
(func << pin_offset);
return DEV_OK;
}
#ifdef CONFIG_PINMUX_DEV
static uint32_t pinmux_dev_set(struct device *dev, uint32_t pin, uint8_t func)
{
const struct pinmux_config *pmux = dev->config->config_info;
/*
* the registers are 32-bit wide, but each pin requires 2 bits
* to set the mode (A, B, C, or D). As such we only get 16
* pins per register... hence the math for the register mask.
*/
uint32_t register_offset = (pin >> 4);
/*
* Now figure out what is the full address for the register
* we are looking for. Add the base register to the register_mask
*/
volatile uint32_t *mux_register =
(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address, register_offset);
/*
* Finally grab the pin offset within the register
*/
uint32_t pin_no = pin % 16;
/*
* The value 3 is used because that is 2-bits for the mode of each
* pin. The value 2 repesents the bits needed for each pin's mode.
*/
uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
uint32_t mode_mask = mode << (pin_no << 1);
(*(mux_register)) = ((*(mux_register)) & ~pin_mask) | mode_mask;
return DEV_OK;
}
static uint32_t pinmux_dev_get(struct device *dev, uint32_t pin, uint8_t *func)
{
const struct pinmux_config *pmux = dev->config->config_info;
/*
* the registers are 32-bit wide, but each pin requires 2 bits
* to set the mode (A, B, C, or D). As such we only get 16
* pins per register... hence the math for the register mask.
*/
uint32_t register_offset = pin >> 4;
/*
* Now figure out what is the full address for the register
* we are looking for. Add the base register to the register_mask
*/
volatile uint32_t *mux_register =
(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address, register_offset);
/*
* Finally grab the pin offset within the register
*/
uint32_t pin_no = pin % 16;
/*
* The value 3 is used because that is 2-bits for the mode of each
* pin. The value 2 repesents the bits needed for each pin's mode.
*/
uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
uint32_t mode_mask = (*(mux_register)) & pin_mask;
uint32_t mode = mode_mask >> (pin_no << 1);
*func = mode;
return DEV_OK;
}
#else
static uint32_t pinmux_dev_set(struct device *dev, uint32_t pin, uint8_t func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(func);
PRINT("ERROR: %s is not enabled", __func__);
return DEV_NOT_CONFIG;
}
static uint32_t pinmux_dev_get(struct device *dev, uint32_t pin, uint8_t *func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(func);
PRINT("ERROR: %s is not enabled", __func__);
return DEV_NOT_CONFIG;
}
#endif /* CONFIG_PINMUX_DEV */
static uint32_t pinmux_dev_pullup(struct device *dev,
uint32_t pin,
uint8_t func)
{
const struct pinmux_config *pmux = dev->config->config_info;
_quark_se_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET, pin, func);
return DEV_OK;
}
static uint32_t pinmux_dev_input(struct device *dev, uint32_t pin, uint8_t func)
{
const struct pinmux_config *pmux = dev->config->config_info;
_quark_se_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin, func);
return DEV_OK;
}
static struct pinmux_driver_api api_funcs = {
.set = pinmux_dev_set,
.get = pinmux_dev_get,
.pullup = pinmux_dev_pullup,
.input = pinmux_dev_input
};
int pinmux_initialize(struct device *port)
{
const struct pinmux_config *pmux = port->config->config_info;
port->driver_api = &api_funcs;
_pinmux_defaults(pmux->base_address);
_pinmux_pullups(pmux->base_address);
return DEV_OK;
}
struct pinmux_config board_pmux = {
.base_address = CONFIG_PINMUX_BASE,
};
DEVICE_INIT(pmux, PINMUX_NAME, &pinmux_initialize,
NULL, &board_pmux,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

17
boards/quark_se_ctb/quark_se_ctb_defconfig
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@ -1,17 +0,0 @@
CONFIG_X86=y
CONFIG_SOC_QUARK_SE=y
CONFIG_BOARD_QUARK_SE_CTB=y
CONFIG_CPU_MINUTEIA=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_IRQ_RISING_EDGE=y
CONFIG_UART_NS16550=y
CONFIG_PRINTK=y
CONFIG_IPM=y
CONFIG_IPM_QUARK_SE=y
CONFIG_IPM_QUARK_SE_MASTER=y
CONFIG_IPM_CONSOLE_RECEIVER=y
CONFIG_ARC_INIT=y
CONFIG_PINMUX=y
CONFIG_SPI_DW_LEVEL_HIGH=y

7
boards/quark_se_sss_ctb/Kconfig
View file

@ -1,7 +0,0 @@
if BOARD_QUARK_SE_SSS_CTB
config BOARD
default "quark_se_sss_ctb"
endif # BOARD_QUARK_SE_SSS_CTB

5
boards/quark_se_sss_ctb/Kconfig.board
View file

@ -1,5 +0,0 @@
config BOARD_QUARK_SE_SSS_CTB
bool "Quark SE Test Board - Sensor Sub System"
select SOC_QUARK_SE_SS
depends on ARC

5
boards/quark_se_sss_ctb/Makefile
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@ -1,5 +0,0 @@
ccflags-y += -I$(srctree)/include/drivers
ccflags-y += -I$(srctree)/drivers
asflags-y := ${ccflags-y}
obj-y += board.o

7
boards/quark_se_sss_ctb/Makefile.board
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@ -1,7 +0,0 @@
FLASH_SCRIPT = openocd.sh
OPENOCD_PRE_CMD = "-c targets 1"
OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_BIN_NAME} 0x40000000"
OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} 0x40000000"
export FLASH_SCRIPT OPENOCD_VERIFY_CMD OPENOCD_LOAD_CMD

21
boards/quark_se_sss_ctb/board.c
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@ -1,21 +0,0 @@
/*
* Copyright (c) 2011-2015, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <nanokernel.h>
#include "board.h"
#include <uart.h>
#include <device.h>
#include <init.h>

22
boards/quark_se_sss_ctb/board.h
View file

@ -1,22 +0,0 @@
/*
* Copyright (c) 2015 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
#endif /* __INC_BOARD_H */

16
boards/quark_se_sss_ctb/quark_se_sss_ctb_defconfig
View file

@ -1,16 +0,0 @@
CONFIG_ARC=y
CONFIG_SOC_QUARK_SE_SS=y
CONFIG_BOARD_QUARK_SE_SSS_CTB=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
CONFIG_XIP=y
CONFIG_NANO_TIMERS=y
CONFIG_PRINTK=y
CONFIG_CPU_ARCEM4=y
CONFIG_CPU_ARCV2=y
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_IPM=y
CONFIG_IPM_QUARK_SE=y
CONFIG_IPM_CONSOLE_SENDER=y
CONFIG_CONSOLE=y

13
boards/quark_se_sss_ctb/support/openocd.cfg
View file

@ -1,13 +0,0 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6010
# oe_n 0x0200
# rst 0x0800
ftdi_channel 0
ftdi_layout_init 0x0000 0xffff
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
source [find board/quark_se.cfg]

2
samples/drivers/aio_dw_comparator/Makefile
View file

@ -1,4 +1,4 @@
BOARD ?= quark_se_ctb
BOARD ?= quark_se_devboard
KERNEL_TYPE = nano
CONF_FILE = prj.conf

5
samples/drivers/gpio/testcase.ini
View file

@ -1,8 +1,5 @@
[test]
build_only = true
tags = drivers
arch_whitelist = x86 arc arm
platform_whitelist = quark_se_ctb quark_se_devboard quark_se_sss_ctb \
arduino_101 arduino_101_sss \
arduino_due
platform_whitelist = quark_se_devboard arduino_101 arduino_101_sss arduino_due

3
samples/drivers/spi_test/testcase.ini
View file

@ -1,6 +1,5 @@
[test]
build_only = true
tags = apps
arch_whitelist = x86
platform_whitelist = galileo arduino_101 quark_se_devboard quark_se_ctb
platform_whitelist = galileo arduino_101 quark_se_devboard

6
scripts/sanity_chk/arches/arc.ini
View file

@ -1,10 +1,6 @@
[arch]
name = arc
platforms = quark_se_sss_ctb arduino_101_sss
[quark_se_sss_ctb]
qemu_support = false
microkernel_support = false
platforms = arduino_101_sss
[arduino_101_sss]
qemu_support = false

5
scripts/sanity_chk/arches/x86.ini
View file

@ -1,6 +1,6 @@
[arch]
name = x86
platforms = qemu_x86 minnowboard galileo quark_se_ctb quark_d2000_crb arduino_101
platforms = qemu_x86 minnowboard galileo quark_d2000_crb arduino_101
[qemu_x86]
qemu_support = true
@ -11,9 +11,6 @@ qemu_support = false
[galileo]
qemu_support = false
[quark_se_ctb]
qemu_support = false
[quark_d2000_crb]
qemu_support = false
microkernel_support = false

2
tests/benchmark/boot_time/microkernel/Makefile
View file

@ -1,6 +1,6 @@
CONF_basic_minuteia = ia32/prj.conf
CONF_quark_d2000_crb = quark_d2000/quark_d2000_prj.conf
CONF_quark_se_ctb = quark_se/quark_se_prj.conf
CONF_quark_se_devboard = quark_se/quark_se_prj.conf
CONF_qemu_x86 = ia32/prj_expert_test.conf
CONF_minnowboard = ia32/prj_expert_test.conf
CONF_galileo = ia32_pci/prj.conf

14
tests/benchmark/boot_time/nanokernel/Makefile
View file

@ -1,10 +1,10 @@
CONF_basic_minuteia = ia32/prj.conf
CONF_quark_d2000_crb= quark_d2000/quark_d2000_prj.conf
CONF_quark_se_ctb = quark_se/quark_se_prj.conf
CONF_qemu_x86 = ia32/prj_expert_test.conf
CONF_galileo = ia32_pci/prj.conf
CONF_minnowboard = ia32/prj_expert_test.conf
CONF_arduino_101 = quark_se/quark_se_prj.conf
CONF_basic_minuteia = ia32/prj.conf
CONF_quark_d2000_crb = quark_d2000/quark_d2000_prj.conf
CONF_quark_se_devboard = quark_se/quark_se_prj.conf
CONF_qemu_x86 = ia32/prj_expert_test.conf
CONF_galileo = ia32_pci/prj.conf
CONF_minnowboard = ia32/prj_expert_test.conf
CONF_arduino_101 = quark_se/quark_se_prj.conf
KERNEL_TYPE = nano
BOARD ?= qemu_x86

2
tests/kernel/test_fifo/testcase.ini
View file

@ -8,4 +8,4 @@ extra_args = KERNEL_TYPE=nano
tags = core
kernel = nano
# Not enough SRAM to run this test on quark SE
platform_exclude = arduino_101_sss quark_se_sss_ctb
platform_exclude = arduino_101_sss

2
tests/kernel/test_lifo/testcase.ini
View file

@ -1,4 +1,4 @@
[test]
tags = core
# Not enough SRAM to run this test on quark SE
platform_exclude = quark_se_sss_ctb arduino_101_sss
platform_exclude = arduino_101_sss

2
tests/kernel/test_sema/nanokernel/testcase.ini
View file

@ -1,4 +1,4 @@
[test]
tags = core
# Not enough SRAM to run this test on quark SE
platform_exclude = quark_se_sss_ctb arduino_101_sss
platform_exclude = arduino_101_sss