riscv32: rename to riscv

With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

CODEOWNERS

@@ -39,10 +39,10 @@
 /arch/x86/                                @andrewboie @gnuless
 /arch/nios2/                              @andrewboie @wentongwu
 /arch/posix/                              @aescolar
-/arch/riscv32/                            @kgugala @pgielda @nategraff-sifive
+/arch/riscv/                              @kgugala @pgielda @nategraff-sifive
 /soc/posix/                               @aescolar
-/soc/riscv32/                             @kgugala @pgielda @nategraff-sifive
-/soc/riscv32/openisa*/                    @MaureenHelm
+/soc/riscv/                               @kgugala @pgielda @nategraff-sifive
+/soc/riscv/openisa*/                      @MaureenHelm
 /arch/x86/core/                           @andrewboie @gnuless
 /arch/x86/core/ia32/crt0.S                @andrewboie @gnuless
 /arch/x86/core/pcie.c                     @gnuless
@@ -88,8 +88,8 @@
 /boards/nios2/altera_max10/               @wentongwu
 /boards/arm/stm32_min_dev/                @cbsiddharth
 /boards/posix/                            @aescolar
-/boards/riscv32/                          @kgugala @pgielda @nategraff-sifive
-/boards/riscv32/rv32m1_vega/              @MaureenHelm
+/boards/riscv/                            @kgugala @pgielda @nategraff-sifive
+/boards/riscv/rv32m1_vega/                @MaureenHelm
 /boards/shields/                          @erwango
 /boards/x86/                              @andrewboie @nashif
 /boards/x86/up_squared/                   @gnuless
@@ -178,8 +178,10 @@
 /dts/arm/nordic/                          @ioannisg @carlescufi
 /dts/arm/nxp/                             @MaureenHelm
 /dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
-/dts/riscv32/rv32m1*                      @MaureenHelm
-/dts/riscv32/riscv32-litex-vexriscv.dtsi  @mateusz-holenko @kgugala @pgielda
+/dts/riscv/microsemi-miv.dtsi             @galak
+/dts/riscv/rv32m1*                        @MaureenHelm
+/dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive
+/dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
 /dts/xtensa/xtensa.dtsi                   @ydamigos
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
@@ -227,7 +229,7 @@
 /include/arch/nios2/                      @andrewboie
 /include/arch/nios2/arch.h                @andrewboie
 /include/arch/posix/                      @aescolar
-/include/arch/riscv32/                    @nategraff-sifive @kgugala @pgielda
+/include/arch/riscv/                      @nategraff-sifive @kgugala @pgielda
 /include/arch/x86/                        @andrewboie @wentongwu
 /include/arch/common/                     @andrewboie @andyross @nashif
 /include/arch/x86/ia32/arch.h             @andrewboie

arch/Kconfig

@@ -41,8 +41,8 @@ config NIOS2
 	select ATOMIC_OPERATIONS_C
 	select HAS_DTS
 
-config RISCV32
-	bool "RISCV32 architecture"
+config RISCV
+	bool "RISCV architecture"
 	select HAS_DTS
 
 config XTENSA

arch/riscv/Kconfig

@@ -4,14 +4,15 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-menu "RISCV32 Options"
-	depends on RISCV32
+menu "RISCV Options"
+	depends on RISCV
 
 config ARCH
 	string
+	default "riscv64" if 64BIT
 	default "riscv32"
 
-menu "RISCV32 Processor Options"
+menu "RISCV Processor Options"
 
 config INCLUDE_RESET_VECTOR
 	bool "Include Reset vector"

arch/riscv/core/fatal.c

@@ -9,8 +9,8 @@
 #include <inttypes.h>
 #include <logging/log_ctrl.h>
 
-FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason,
-					 const z_arch_esf_t *esf)
+FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
+				       const z_arch_esf_t *esf)
 {
 	if (esf != NULL) {
 		z_fatal_print("Faulting instruction address = 0x%08x",
@@ -61,5 +61,5 @@ FUNC_NORETURN void _Fault(const z_arch_esf_t *esf)
 	z_fatal_print("Exception cause %s (%d)", cause_str(mcause),
 		      (int)mcause);
 
-	z_riscv32_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+	z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
 }

arch/riscv/core/irq_manage.c

@@ -24,7 +24,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused)
 			      riscv_plic_get_irq());
 	}
 #endif
-	z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
+	z_riscv_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
 }
 
 #ifdef CONFIG_DYNAMIC_INTERRUPTS

arch/riscv/include/kernel_arch_data.h

@@ -9,11 +9,11 @@
  * @brief Private kernel definitions
  *
  * This file contains private kernel structures definitions and various
- * other definitions for the RISCV32 processor architecture.
+ * other definitions for the RISCV processor architecture.
  */
 
-#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_
-#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_
+#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_
+#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -35,4 +35,4 @@ extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_ */
+#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_ */

arch/riscv/include/kernel_arch_func.h

@@ -9,11 +9,11 @@
  * @brief Private kernel definitions
  *
  * This file contains private kernel function/macro definitions and various
- * other definitions for the RISCV32 processor architecture.
+ * other definitions for the RISCV processor architecture.
  */
 
-#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_
-#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_
+#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
+#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
 
 #include <soc.h>
 
@@ -37,8 +37,8 @@ z_set_thread_return_value(struct k_thread *thread, unsigned int value)
 	thread->arch.swap_return_value = value;
 }
 
-FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason,
-					 const z_arch_esf_t *esf);
+FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
+				       const z_arch_esf_t *esf);
 
 #define z_is_in_isr() (_kernel.nested != 0U)
 
@@ -52,4 +52,4 @@ int z_irq_do_offload(void);
 }
 #endif
 
-#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_ */
+#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ */

arch/riscv/include/kernel_arch_thread.h

@@ -16,8 +16,8 @@
  * necessary to instantiate instances of struct k_thread.
  */
 
-#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_
-#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_
+#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_
+#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -52,5 +52,4 @@ typedef struct _thread_arch _thread_arch_t;
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_ */
-
+#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ */

arch/riscv/include/offsets_short_arch.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_
-#define ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_
+#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_
+#define ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_
 
 #include <offsets.h>
 
@@ -61,4 +61,4 @@
 
 /* end - threads */
 
-#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
+#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ */

boards/index.rst

@@ -19,5 +19,5 @@ under :zephyr_file:`doc/templates/board.tmpl`
    nios2/index.rst
    xtensa/index.rst
    posix/index.rst
-   riscv32/index.rst
+   riscv/index.rst
    shields/index.rst

boards/riscv/hifive1/doc/index.rst

@@ -56,4 +56,3 @@ Debugging
 =========
 
 Refer to the detailed overview about :ref:`application_debugging`.
-

boards/riscv/hifive1/hifive1.dts

@@ -94,4 +94,3 @@
 	status = "okay";
 	clock-frequency = <16000000>;
 };
-

boards/riscv/hifive1/hifive1_defconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_BOARD_HIFIVE1=y

boards/riscv/hifive1_revb/doc/index.rst

@@ -43,4 +43,3 @@ Debugging
 =========
 
 Refer to the detailed overview about :ref:`application_debugging`.
-

boards/riscv/hifive1_revb/hifive1_revb.dts

@@ -98,4 +98,3 @@
 	input-frequency = <16000000>;
 	clock-frequency = <100000>;
 };
-

boards/riscv/hifive1_revb/hifive1_revb_defconfig

@@ -1,4 +1,4 @@
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_BOARD_HIFIVE1_REVB=y

boards/riscv/index.rst

@@ -1,6 +1,6 @@
-.. _boards-riscv32:
+.. _boards-riscv:
 
-RISCV32 Boards
+RISCV Boards
 ##############
 
 .. toctree::

boards/riscv/litex_vexriscv/litex_vexriscv_defconfig

@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y
 CONFIG_BOARD_LITEX_VEXRISCV=y
 CONFIG_VEXRISCV_LITEX_IRQ=y

boards/riscv/m2gl025_miv/doc/index.rst

@@ -64,4 +64,3 @@ Debugging
 =========
 
 Refer to the detailed overview of :ref:`application_debugging`.
-

boards/riscv/m2gl025_miv/m2gl025_miv_defconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_SERIES_RISCV32_MIV=y
 CONFIG_SOC_RISCV32_MIV=y
 CONFIG_BOARD_M2GL025_MIV=y

boards/riscv/qemu_riscv32/board.cmake

@@ -2,6 +2,7 @@
 
 set(EMU_PLATFORM qemu)
 
+set(QEMU_binary_suffix riscv32)
 set(QEMU_CPU_TYPE_${ARCH} riscv32)
 
 set(QEMU_FLAGS_${ARCH}

boards/riscv/qemu_riscv32/qemu_riscv32.dts

@@ -46,4 +46,3 @@
 		spi-max-frequency = <0>;
 	};
 };
-

boards/riscv/qemu_riscv32/qemu_riscv32_defconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
 CONFIG_BOARD_QEMU_RISCV32=y

boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
 CONFIG_SOC_OPENISA_RV32M1_RI5CY=y
 CONFIG_BOARD_RV32M1_VEGA=y

boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig

@@ -1,4 +1,4 @@
-CONFIG_RISCV32=y
+CONFIG_RISCV=y
 CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
 CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y
 CONFIG_BOARD_RV32M1_VEGA=y

cmake/toolchain/xtools/target.cmake

@@ -9,7 +9,7 @@ endif()
 
 set(CROSS_COMPILE_TARGET_arm         arm-zephyr-eabi)
 set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
-set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
+set(CROSS_COMPILE_TARGET_riscv   riscv32-zephyr-elf)
 set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)
 set(CROSS_COMPILE_TARGET_xtensa   xtensa-zephyr-elf)
 set(CROSS_COMPILE_TARGET_arc         arc-zephyr-elf)

cmake/toolchain/zephyr/0.10.0/target.cmake

@@ -9,7 +9,7 @@ endif()
 
 set(CROSS_COMPILE_TARGET_arm         arm-zephyr-eabi)
 set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
-set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
+set(CROSS_COMPILE_TARGET_riscv   riscv32-zephyr-elf)
 set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)
 set(CROSS_COMPILE_TARGET_xtensa   xtensa-zephyr-elf)
 set(CROSS_COMPILE_TARGET_arc         arc-zephyr-elf)

cmake/toolchain/zephyr/0.10.1/target.cmake

@@ -9,7 +9,7 @@ endif()
 
 set(CROSS_COMPILE_TARGET_arm         arm-zephyr-eabi)
 set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
-set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
+set(CROSS_COMPILE_TARGET_riscv   riscv32-zephyr-elf)
 set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)
 set(CROSS_COMPILE_TARGET_xtensa   xtensa-zephyr-elf)
 set(CROSS_COMPILE_TARGET_arc         arc-zephyr-elf)

doc/conf.py

@@ -402,10 +402,18 @@ html_redirect_pages = [
 		('boards/nios2/altera_max10/doc/board', 'boards/nios2/altera_max10/doc/index'),
 		('boards/nios2/qemu_nios2/doc/board', 'boards/nios2/qemu_nios2/doc/index'),
 		('boards/posix/native_posix/doc/board', 'boards/posix/native_posix/doc/index'),
-		('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv32/hifive1/doc/index'),
-		('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv32/m2gl025_miv/doc/index'),
-		('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv32/qemu_riscv32/doc/index'),
-		('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv32/zedboard_pulpino/doc/index'),
+		('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv/hifive1/doc/index'),
+		('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv/m2gl025_miv/doc/index'),
+		('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv/qemu_riscv32/doc/index'),
+		('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv/zedboard_pulpino/doc/index'),
+                ('boards/riscv32/hifive1/doc/index', 'boards/riscv/hifive1/doc/index'),
+                ('boards/riscv32/hifive1_revb/doc/index', 'boards/riscv/hifive1_revb/doc/index'),
+                ('boards/riscv32/litex_vexriscv/doc/litex_vexriscv', 'boards/riscv/litex_vexriscv/doc/litex_vexriscv'),
+                ('boards/riscv32/m2gl025_miv/doc/index', 'boards/riscv/m2gl025_miv/doc/index'),
+                ('boards/riscv32/qemu_riscv32/doc/index', 'boards/riscv/qemu_riscv32/doc/index'),
+                ('boards/riscv32/rv32m1_vega/doc/index', 'boards/riscv/rv32m1_vega/doc/index'),
+		('boards/x86/arduino_101/doc/board', 'boards/x86/arduino_101/doc/index'),
+		('boards/x86/galileo/doc/galileo', 'boards/x86/galileo/doc/index'),
 		('boards/x86/minnowboard/doc/minnowboard', 'boards/x86/minnowboard/doc/index'),
 		('boards/x86/qemu_x86/doc/board', 'boards/x86/qemu_x86/doc/index'),
 		('boards/x86/tinytile/doc/board', 'boards/x86/tinytile/doc/index'),

drivers/interrupt_controller/plic.c

@@ -100,7 +100,7 @@ int riscv_plic_irq_is_enabled(u32_t irq)
  * @brief Set priority of a riscv PLIC-specific interrupt line
  *
  * This routine set the priority of a RISCV PLIC-specific interrupt line.
- * riscv_plic_irq_set_prio is called by riscv32 Z_ARCH_IRQ_CONNECT to set
+ * riscv_plic_irq_set_prio is called by riscv Z_ARCH_IRQ_CONNECT to set
  * the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
  * @param irq IRQ number for which to set priority
  *

dts/riscv/rv32m1_ri5cy.dtsi

@@ -3,7 +3,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <riscv32/rv32m1.dtsi>
+#include <riscv/rv32m1.dtsi>
 
 / {
 	aliases {

dts/riscv/rv32m1_zero_riscy.dtsi

@@ -3,7 +3,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <riscv32/rv32m1.dtsi>
+#include <riscv/rv32m1.dtsi>
 
 / {
 	aliases {

include/arch/cpu.h

@@ -19,8 +19,8 @@
 #include <arch/arc/arch.h>
 #elif defined(CONFIG_NIOS2)
 #include <arch/nios2/arch.h>
-#elif defined(CONFIG_RISCV32)
-#include <arch/riscv32/arch.h>
+#elif defined(CONFIG_RISCV)
+#include <arch/riscv/arch.h>
 #elif defined(CONFIG_XTENSA)
 #include <arch/xtensa/arch.h>
 #elif defined(CONFIG_ARCH_POSIX)

include/arch/riscv/arch.h

@@ -7,13 +7,13 @@
 
 /**
  * @file
- * @brief RISCV32 specific kernel interface header
- * This header contains the RISCV32 specific kernel interface.  It is
+ * @brief RISCV specific kernel interface header
+ * This header contains the RISCV specific kernel interface.  It is
  * included by the generic kernel interface header (arch/cpu.h)
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_ARCH_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV32_ARCH_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_
 
 #include "exp.h"
 #include <arch/common/sys_io.h>
@@ -37,7 +37,7 @@ extern "C" {
 #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN)
 #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN)
 
-/* macros convert value of it's argument to a string */
+/* macros convert value of its argument to a string */
 #define DO_TOSTR(s) #s
 #define TOSTR(s) DO_TOSTR(s)
 
@@ -147,7 +147,7 @@ extern u32_t z_timer_cycle_get_32(void);
 #endif /*_ASMLANGUAGE */
 
 #if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
-#include <arch/riscv32/riscv-privilege/asm_inline.h>
+#include <arch/riscv/riscv-privilege/asm_inline.h>
 #endif
 
 #ifdef __cplusplus

include/arch/riscv/common/linker.ld

@@ -8,7 +8,7 @@
  * @file
  * @brief Linker command/script file
  *
- * Generic Linker script for the riscv32 platform
+ * Generic Linker script for the riscv platform
  */
 
 #define _LINKER

include/arch/riscv/exp.h

@@ -7,13 +7,13 @@
 
 /**
  * @file
- * @brief RISCV32 public exception handling
+ * @brief RISCV public exception handling
  *
- * RISCV32-specific kernel exception handling interface.
+ * RISCV-specific kernel exception handling interface.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -81,4 +81,4 @@ typedef struct soc_esf soc_esf_t;
 }
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ */

include/arch/riscv/riscv-privilege/asm_inline.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_
 
 /*
  * The file must not be included directly
@@ -14,9 +14,9 @@
  */
 
 #if defined(__GNUC__)
-#include <arch/riscv32/riscv-privilege/asm_inline_gcc.h>
+#include <arch/riscv/riscv-privilege/asm_inline_gcc.h>
 #else
 #error "Supports only GNU C compiler"
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_ */

include/arch/riscv/riscv-privilege/asm_inline_gcc.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -28,4 +28,4 @@ extern "C" {
 }
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ */

include/linker/linker-tool-gcc.h

@@ -34,9 +34,13 @@
 	#endif
 #elif defined(CONFIG_NIOS2)
 	OUTPUT_FORMAT("elf32-littlenios2", "elf32-bignios2", "elf32-littlenios2")
-#elif defined(CONFIG_RISCV32)
+#elif defined(CONFIG_RISCV)
 	OUTPUT_ARCH("riscv")
+#ifdef CONFIG_64BIT
+	OUTPUT_FORMAT("elf64-littleriscv")
+#else
 	OUTPUT_FORMAT("elf32-littleriscv")
+#endif
 #elif defined(CONFIG_XTENSA)
 	/* Not needed */
 #elif defined(CONFIG_ARCH_POSIX)