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irq: cortex-r: Fix wrong irq enabling

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In the cortex-r port we are currently using GIC as a fake cascade
controller hooked to a fake parent IRQ #0. And in gic_init() we use
IRQ_CONNECT() to connect this dummy IRQ.

Unfortunately this value is shifted and offset when calling
irq_set_priority_next_level() that tries to set the IRQ priority on a
value of 0xffffffff.

This value is offset again in gic_irq_set_priority() that actually sets
the priority on the PPI #31.

Fix this avoiding to set any priority for IRQ #0.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2019-10-30 13:30:04 +00:00 committed by Andrew Boie
parent 626f96ec30
commit 1f6d4e2705
1 changed files with 3 additions and 0 deletions
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3
arch/arm/core/irq_manage.c
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@ -135,6 +135,9 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
{
struct device *dev = _sw_isr_table[0].arg;
if (irq == 0)
return;
irq_set_priority_next_level(dev, (irq >> 8) - 1, prio, flags);
}