soc: gd32a50x: introduce gd32a50x soc series

soc: gd32a50x: introduce gd32a50x soc series

Signed-off-by: YuLong Yao <feilongphone@gmail.com>

modules/hal_gigadevice/CMakeLists.txt

@@ -46,6 +46,11 @@ if(${CONFIG_SOC_SERIES_GD32E50X})
   endif()
 endif()
 
+# GD32A50X series HAL public headers require extra definitions
+if(${CONFIG_SOC_SERIES_GD32A50X})
+  zephyr_compile_definitions(GD32A50X)
+endif()
+
 # Global includes to be used outside hal_gigadevice
 zephyr_include_directories(${gd32_soc_sys_dir}/include)
 zephyr_include_directories(${gd32_std_dir}/include)

soc/arm/gigadevice/gd32a50x/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)

soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32a503

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "gd32a503"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config NUM_IRQS
+	default 82

soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32A50X
+
+source "soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32*"
+
+config SOC_SERIES
+	default "gd32a50x"
+
+endif # SOC_SERIES_GD32A50X

soc/arm/gigadevice/gd32a50x/Kconfig.series

@@ -0,0 +1,15 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32A50X
+	bool "GigaDevice GD32A50X series Cortex-M33 MCU"
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M33
+	select SOC_FAMILY_GD32_ARM
+	select GD32_HAS_AF_PINMUX
+	select GD32_HAS_IRC_40K
+	select PLATFORM_SPECIFIC_INIT
+	help
+	  Enable support for GigaDevice GD32A50X MCU series

soc/arm/gigadevice/gd32a50x/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32A50X MCU Selection"
+	depends on SOC_SERIES_GD32A50X
+
+	config SOC_GD32A503
+		bool "gd32a503"
+
+endchoice

soc/arm/gigadevice/gd32a50x/gd32_regs.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_
+#define SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_
+
+#include <zephyr/sys/util_macro.h>
+
+/* RCU */
+#define RCU_CFG0_OFFSET      0x04U
+#define RCU_AHBEN_OFFSET     0x14U
+#define RCU_APB1EN_OFFSET    0x1CU
+#define RCU_APB2EN_OFFSET    0x18U
+#define RCU_CFG1_OFFSET      0x2CU
+#define RCU_CFG2_OFFSET      0x30U
+
+#define RCU_CFG0_AHBPSC_POS  4U
+#define RCU_CFG0_AHBPSC_MSK  (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
+#define RCU_CFG0_APB1PSC_POS 8U
+#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
+#define RCU_CFG0_APB2PSC_POS 11U
+#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
+
+#endif /* SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_ */

soc/arm/gigadevice/gd32a50x/linker.ld

@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/gigadevice/gd32a50x/soc.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/irq.h>
+
+/* initial ecc memory */
+void z_arm_platform_init(void)
+{
+	register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram));
+	register unsigned r1 __asm("r1") =
+		DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_sram));
+
+	for (; r0 < r1; r0 += 4) {
+		*(unsigned int *)r0 = 0;
+	}
+}
+
+static int gd32a50x_soc_init(const struct device *dev)
+{
+	uint32_t key;
+
+	ARG_UNUSED(dev);
+
+	key = irq_lock();
+
+	SystemInit();
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gd32a50x_soc_init, PRE_KERNEL_1, 0);

soc/arm/gigadevice/gd32a50x/soc.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_
+#define _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <gd32a50x.h>
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_ */