dts: arm: gigadevice: introduce dac for gd32 series soc

Add DAC for gd32f4xx and gd32f350xx.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
This commit is contained in:
HaiLong Yang 2021-12-14 22:46:41 +08:00 committed by Carles Cufí
parent de53e7f932
commit 222f42f2e8
5 changed files with 68 additions and 2 deletions

View file

@ -0,0 +1,22 @@
/*
* Copyright (c) 2021 BrainCo Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
/ {
soc {
dac: dac@40007400 {
compatible = "gd,gd32-dac";
reg = <0x40007400 0x400>;
rcu-periph-clock = <0x71d>;
num-channels = <1>;
label = "DAC";
status = "disabled";
#io-channel-cells = <1>;
};
};
};

View file

@ -5,7 +5,7 @@
*/
#include <mem.h>
#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
#include <gigadevice/gd32f3x0/gd32f350.dtsi>
/ {
soc {

View file

@ -5,7 +5,7 @@
*/
#include <mem.h>
#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
#include <gigadevice/gd32f3x0/gd32f350.dtsi>
/ {
soc {

View file

@ -118,6 +118,16 @@
label = "USART_7";
};
dac: dac@40007400 {
compatible = "gd,gd32-dac";
reg = <0x40007400 0x400>;
rcu-periph-clock = <0x101d>;
num-channels = <2>;
label = "DAC";
status = "disabled";
#io-channel-cells = <1>;
};
pinctrl: pin-controller@40020000 {
compatible = "gd,gd32-pinctrl-af";
reg = <0x40020000 0x2400>;

View file

@ -0,0 +1,34 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
description: GigaDevice GD32 series DAC module
compatible: "gd,gd32-dac"
include: [dac-controller.yaml, pinctrl-device.yaml]
properties:
reg:
required: true
rcu-periph-clock:
type: int
description: Reset Control Unit Peripheral Clock ID
required: true
num-channels:
type: int
description: Number of DAC output channels
required: true
reset-val:
type: int
default: 0
description: Reset value of DAC output. Defaults to 0, the SoC default.
required: false
"#io-channel-cells":
const: 1
io-channel-cells:
- output