dts: arm: gigadevice: introduce dac for gd32 series soc
Add DAC for gd32f4xx and gd32f350xx. Signed-off-by: HaiLong Yang <cameledyang@pm.me>
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dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi
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22
dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi
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/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
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/ {
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soc {
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dac: dac@40007400 {
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compatible = "gd,gd32-dac";
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reg = <0x40007400 0x400>;
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rcu-periph-clock = <0x71d>;
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num-channels = <1>;
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label = "DAC";
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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};
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@ -5,7 +5,7 @@
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*/
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#include <mem.h>
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#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
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#include <gigadevice/gd32f3x0/gd32f350.dtsi>
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/ {
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soc {
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@ -5,7 +5,7 @@
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*/
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#include <mem.h>
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#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
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#include <gigadevice/gd32f3x0/gd32f350.dtsi>
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/ {
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soc {
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@ -118,6 +118,16 @@
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label = "USART_7";
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};
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dac: dac@40007400 {
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compatible = "gd,gd32-dac";
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reg = <0x40007400 0x400>;
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rcu-periph-clock = <0x101d>;
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num-channels = <2>;
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label = "DAC";
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status = "disabled";
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#io-channel-cells = <1>;
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};
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pinctrl: pin-controller@40020000 {
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compatible = "gd,gd32-pinctrl-af";
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reg = <0x40020000 0x2400>;
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34
dts/bindings/dac/gd,gd32-dac.yaml
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dts/bindings/dac/gd,gd32-dac.yaml
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: GigaDevice GD32 series DAC module
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compatible: "gd,gd32-dac"
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include: [dac-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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rcu-periph-clock:
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type: int
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description: Reset Control Unit Peripheral Clock ID
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required: true
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num-channels:
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type: int
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description: Number of DAC output channels
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required: true
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reset-val:
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type: int
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default: 0
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description: Reset value of DAC output. Defaults to 0, the SoC default.
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required: false
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"#io-channel-cells":
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const: 1
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io-channel-cells:
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- output
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