From 2236eaf52c6b148eab8cf164f29dcccbe5c9b351 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 6 Dec 2023 11:02:32 -0600 Subject: [PATCH] drivers: sdhc: imx_usdhc: add explicit fallthrough to I/O timing setup DDR50/DDR52 modes should use PINCTRL_STATE_SLOW (50MHz), so the lack of a break statement after enabling DDR mode is expected. Add an explicit __fallthrough to resolve the issue flagged by coverity scan Fixes #65324 Signed-off-by: Daniel DeGrasse --- drivers/sdhc/imx_usdhc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/sdhc/imx_usdhc.c b/drivers/sdhc/imx_usdhc.c index e5954b6afb..84f8f2aee3 100644 --- a/drivers/sdhc/imx_usdhc.c +++ b/drivers/sdhc/imx_usdhc.c @@ -404,6 +404,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios) case SDHC_TIMING_DDR52: /* Enable DDR mode */ USDHC_EnableDDRMode(cfg->base, true, 0); + __fallthrough; case SDHC_TIMING_SDR12: case SDHC_TIMING_SDR25: pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW);